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Searched refs:regTypes (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/mlir/lib/Dialect/LLVMIR/IR/
H A DNVVMDialect.cpp132 SmallVector<Type, 4> regTypes; in print() local
156 regTypes.push_back(this->getOperand(operandIdx).getType()); in print()
160 inferOperandMMAType(regTypes.back(), /*isAccum=*/fragIdx >= 2); in print()
249 SmallVector<Type> regTypes; in parse() member
296 frag.regTypes.resize(frag.regs.size(), iter.value()); in parse()
297 if (failed(parser.resolveOperands(frag.regs, frag.regTypes, in parse()
301 inferOperandMMAType(frag.regTypes[0], /*isAccum=*/iter.index() < 2); in parse()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.td19 class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
20 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td754 list<ValueType> regTypes,
774 SIRegisterClass<"AMDGPU", regTypes, 32,
800 class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :
801 SIRegisterClass<"AMDGPU", regTypes, 32, regList> {
812 multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {
815 def "" : VRegClassBase<numRegs, regTypes, regList>;
818 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)>;
837 def "" : VRegClassBase<numRegs, regTypes, regList>;
888 multiclass AVRegClass<int numRegs, list<ValueType> regTypes,
892 def "" : VRegClassBase<numRegs, regTypes, (add vregList, aregList)>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.td17 class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
18 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
/llvm-project-15.0.7/llvm/test/TableGen/
H A DTargetInstrSpec.td42 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
43 list<ValueType> RegTypes = regTypes;
H A Dcast.td41 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
42 list<ValueType> RegTypes = regTypes;
H A DSlice.td35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
36 list<ValueType> RegTypes = regTypes;
H A DMultiPat.td45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
46 list<ValueType> RegTypes = regTypes;
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td85 class MxRegClass<list<ValueType> regTypes, int alignment, dag regList>
86 : RegisterClass<"M68k", regTypes, alignment, regList>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td482 class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
484 regTypes,
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td281 class GPR32Class<list<ValueType> regTypes> :
282 RegisterClass<"Mips", regTypes, 32, (add
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td215 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
229 list<ValueType> RegTypes = regTypes;
/llvm-project-15.0.7/llvm/docs/
H A DWritingAnLLVMBackend.rst484 list<ValueType> regTypes, int alignment, dag regList> {
486 list<ValueType> RegTypes = regTypes;