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Searched refs:regClass (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td155 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
203 def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
213 (outs regClass:$vdst),
216 !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
241 def "" : FLAT_Store_Pseudo<opName, regClass, 1>,
243 def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1>,
296 def "" : FLAT_Global_Store_AddTid_Pseudo<opName, regClass>,
314 (outs getLdStRegisterOperand<regClass>.ret:$vdst),
385 def "" : FLAT_Scratch_Store_Pseudo<opName, regClass>,
387 def _SADDR : FLAT_Scratch_Store_Pseudo<opName, regClass, 1>,
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H A DSIWholeQuadMode.cpp1454 const TargetRegisterClass *regClass = in lowerCopyInstrs() local
1457 regClass = TRI->getSubRegClass(regClass, SubReg); in lowerCopyInstrs()
1459 const unsigned MovOp = TII->getMovOpcode(regClass); in lowerCopyInstrs()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h764 int16_t regClass = Desc.OpInfo[OpNo].RegClass; in getRegNumForOperand() local
765 switch (regClass) { in getRegNumForOperand()