| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/RISCV/ |
| H A D | reduce-max.ll | 236 declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>)
237 declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
238 declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1>)
239 declare i1 @llvm.vector.reduce.umax.v8i1(<8 x i1>)
244 declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8>)
245 declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)
246 declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
247 declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
276 declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>)
277 declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
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| H A D | reduce-min.ll | 235 declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>)
236 declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
237 declare i1 @llvm.vector.reduce.umin.v4i1(<4 x i1>)
238 declare i1 @llvm.vector.reduce.umin.v8i1(<8 x i1>)
243 declare i8 @llvm.vector.reduce.umin.v1i8(<1 x i8>)
244 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
245 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
246 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
275 declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>)
276 declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
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| H A D | reduce-and.ll | 126 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
127 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
128 declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
129 declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
130 declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
131 declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
132 declare i1 @llvm.vector.reduce.and.v64i1(<64 x i1>)
137 declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8>)
138 declare i8 @llvm.vector.reduce.and.v2i8(<2 x i8>)
139 declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
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| H A D | reduce-or.ll | 126 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
127 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
128 declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
129 declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
130 declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
131 declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
132 declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
137 declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)
138 declare i8 @llvm.vector.reduce.or.v2i8(<2 x i8>)
139 declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
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| H A D | reduce-add.ll | 120 declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>)
121 declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>)
122 declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1>)
123 declare i1 @llvm.vector.reduce.add.v8i1(<8 x i1>)
124 declare i1 @llvm.vector.reduce.add.v16i1(<16 x i1>)
125 declare i1 @llvm.vector.reduce.add.v32i1(<32 x i1>)
126 declare i1 @llvm.vector.reduce.add.v64i1(<64 x i1>)
128 declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8>)
129 declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
130 declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
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| H A D | reduce-xor.ll | 120 declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
121 declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
122 declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
123 declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
124 declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)
125 declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>)
126 declare i1 @llvm.vector.reduce.xor.v64i1(<64 x i1>)
128 declare i8 @llvm.vector.reduce.xor.v1i8(<1 x i8>)
129 declare i8 @llvm.vector.reduce.xor.v2i8(<2 x i8>)
130 declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
[all …]
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| H A D | reduce-fadd.ll | 136 declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
137 declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
138 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
139 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
140 declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>)
141 declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
142 declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>)
144 declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
145 declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
146 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
[all …]
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| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | reduce-minmax.ll | 239 declare i8 @llvm.vector.reduce.umin.v1i8(<1 x i8>)
240 declare i8 @llvm.vector.reduce.umin.v3i8(<3 x i8>)
241 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
242 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
256 declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8>)
257 declare i8 @llvm.vector.reduce.umax.v3i8(<3 x i8>)
258 declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
259 declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
273 declare i8 @llvm.vector.reduce.smin.v1i8(<1 x i8>)
274 declare i8 @llvm.vector.reduce.smin.v3i8(<3 x i8>)
[all …]
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| H A D | reduce-and.ll | 4 define void @reduce() {
5 ; CHECK-LABEL: 'reduce'
59 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
60 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
61 declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
62 declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
63 declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
67 declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8>)
68 declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8>)
69 declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
[all …]
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| H A D | reduce-or.ll | 4 define void @reduce() {
5 ; CHECK-LABEL: 'reduce'
59 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
60 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
61 declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
62 declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
63 declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
67 declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)
68 declare i8 @llvm.vector.reduce.or.v3i8(<3 x i8>)
69 declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
[all …]
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| H A D | reduce-xor.ll | 4 define void @reduce() {
5 ; CHECK-LABEL: 'reduce'
59 declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
60 declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
61 declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
62 declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
63 declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)
67 declare i8 @llvm.vector.reduce.xor.v1i8(<1 x i8>)
68 declare i8 @llvm.vector.reduce.xor.v3i8(<3 x i8>)
69 declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
[all …]
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| H A D | reduce-add.ll | 4 define void @reduce() {
5 ; CHECK-LABEL: 'reduce'
43 declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8>)
44 declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8>)
45 declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
46 declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
47 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
48 declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)
49 declare i8 @llvm.vector.reduce.add.v64i8(<64 x i8>)
50 declare i16 @llvm.vector.reduce.add.v2i16(<2 x i16>)
[all …]
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| H A D | reduce-fadd.ll | 77 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
78 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
79 declare half @llvm.vector.reduce.fadd.v11f16(half, <11 x half>)
80 declare half @llvm.vector.reduce.fadd.v13f16(half, <13 x half>)
82 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
83 declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
84 declare float @llvm.vector.reduce.fadd.v13f32(float, <13 x float>)
85 declare float @llvm.vector.reduce.fadd.v5f32(float, <5 x float>)
87 declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>)
88 declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>)
[all …]
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| /llvm-project-15.0.7/llvm/test/Bitcode/ |
| H A D | upgrade-vecreduce-intrinsics.ll | 101 ; CHECK: declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
106 declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32>)
107 ; CHECK: declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
109 declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
110 ; CHECK: declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
112 declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
113 ; CHECK: declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
116 ; CHECK: declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
119 ; CHECK: declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
122 ; CHECK: declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
[all …]
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| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/ |
| H A D | reduce-smin.ll | 152 declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)
153 declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
154 declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
155 declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>)
158 declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)
171 declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>)
172 declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
173 declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
174 declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
175 declare i8 @llvm.vector.reduce.smin.v32i8(<32 x i8>)
[all …]
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| H A D | reduce-umax.ll | 152 declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)
153 declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
154 declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
155 declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
158 declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)
171 declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)
172 declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
173 declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
174 declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
175 declare i8 @llvm.vector.reduce.umax.v32i8(<32 x i8>)
[all …]
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| H A D | reduce-smax.ll | 152 declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>)
153 declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)
154 declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)
155 declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>)
158 declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)
171 declare i8 @llvm.vector.reduce.smax.v2i8(<2 x i8>)
172 declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
173 declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)
174 declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)
175 declare i8 @llvm.vector.reduce.smax.v32i8(<32 x i8>)
[all …]
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| H A D | reduce-umin.ll | 152 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
154 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
155 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
158 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
171 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
174 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
175 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
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| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/ |
| H A D | reduce-xor.ll | 274 declare i8 @llvm.vector.reduce.xor.v2i8(<2 x i8>)
275 declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
276 declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
277 declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
278 declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
279 declare i8 @llvm.vector.reduce.xor.v64i8(<64 x i8>)
282 declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
283 declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
284 declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
285 declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
[all …]
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| H A D | reduce-or.ll | 252 declare i8 @llvm.vector.reduce.or.v2i8(<2 x i8>)
253 declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
254 declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
255 declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
256 declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
257 declare i8 @llvm.vector.reduce.or.v64i8(<64 x i8>)
260 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
261 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
262 declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
263 declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
[all …]
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| H A D | reduce-and.ll | 252 declare i8 @llvm.vector.reduce.and.v2i8(<2 x i8>)
253 declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
254 declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
255 declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
256 declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)
257 declare i8 @llvm.vector.reduce.and.v64i8(<64 x i8>)
260 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
261 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
262 declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
263 declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
[all …]
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| H A D | reduce-mul.ll | 276 declare i64 @llvm.vector.reduce.mul.v1i64(<1 x i64>)
277 declare i64 @llvm.vector.reduce.mul.v2i64(<2 x i64>)
278 declare i64 @llvm.vector.reduce.mul.v4i64(<4 x i64>)
279 declare i64 @llvm.vector.reduce.mul.v8i64(<8 x i64>)
282 declare i32 @llvm.vector.reduce.mul.v2i32(<2 x i32>)
295 declare i8 @llvm.vector.reduce.mul.v2i8(<2 x i8>)
296 declare i8 @llvm.vector.reduce.mul.v4i8(<4 x i8>)
297 declare i8 @llvm.vector.reduce.mul.v8i8(<8 x i8>)
298 declare i8 @llvm.vector.reduce.mul.v16i8(<16 x i8>)
299 declare i8 @llvm.vector.reduce.mul.v32i8(<32 x i8>)
[all …]
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| H A D | reduce-umax.ll | 307 declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umax.v32i8(<32 x i8>)
[all …]
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| H A D | reduce-smin.ll | 307 declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.smin.v32i8(<32 x i8>)
[all …]
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| H A D | reduce-umin.ll | 307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
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