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Searched refs:read_register (Results 1 – 25 of 73) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dreg-by-name.ll7 declare i32 @llvm.read_register.i32(metadata) #2
8 declare i64 @llvm.read_register.i64(metadata) #2
15 %0 = call i32 @llvm.read_register.i32(metadata !0)
25 %0 = call i32 @llvm.read_register.i32(metadata !1)
35 %0 = call i32 @llvm.read_register.i32(metadata !2)
45 %0 = call i32 @llvm.read_register.i32(metadata !3)
55 %0 = call i32 @llvm.read_register.i32(metadata !4)
65 %0 = call i32 @llvm.read_register.i32(metadata !5)
75 %0 = call i32 @llvm.read_register.i32(metadata !6)
85 %0 = call i32 @llvm.read_register.i32(metadata !7)
[all …]
H A Dnamedreg.ll4 %0 = call i32 @llvm.read_register.i32(metadata !0)
7 declare i32 @llvm.read_register.i32(metadata) #1
11 %0 = call i32 @llvm.read_register.i32(metadata !1)
17 %0 = call i32 @llvm.read_register.i32(metadata !2)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dspecial-reg-v8m-main.ll35 %0 = call i32 @llvm.read_register.i32(metadata !0)
36 %1 = call i32 @llvm.read_register.i32(metadata !4)
38 %2 = call i32 @llvm.read_register.i32(metadata !8)
40 %3 = call i32 @llvm.read_register.i32(metadata !12)
42 %4 = call i32 @llvm.read_register.i32(metadata !16)
44 %5 = call i32 @llvm.read_register.i32(metadata !17)
46 %6 = call i32 @llvm.read_register.i32(metadata !18)
48 %7 = call i32 @llvm.read_register.i32(metadata !19)
50 %8 = call i32 @llvm.read_register.i32(metadata !20)
52 %9 = call i32 @llvm.read_register.i32(metadata !21)
[all …]
H A Dspecial-reg-v8m-base.ll28 %0 = call i32 @llvm.read_register.i32(metadata !0)
29 %1 = call i32 @llvm.read_register.i32(metadata !4)
31 %2 = call i32 @llvm.read_register.i32(metadata !8)
33 %3 = call i32 @llvm.read_register.i32(metadata !12)
35 %4 = call i32 @llvm.read_register.i32(metadata !16)
37 %5 = call i32 @llvm.read_register.i32(metadata !17)
39 %6 = call i32 @llvm.read_register.i32(metadata !18)
41 %7 = call i32 @llvm.read_register.i32(metadata !19)
43 %8 = call i32 @llvm.read_register.i32(metadata !20)
45 %9 = call i32 @llvm.read_register.i32(metadata !21)
[all …]
H A Dspecial-reg-mcore.ll26 %0 = call i32 @llvm.read_register.i32(metadata !0)
27 %1 = call i32 @llvm.read_register.i32(metadata !4)
29 %2 = call i32 @llvm.read_register.i32(metadata !8)
31 %3 = call i32 @llvm.read_register.i32(metadata !12)
33 %4 = call i32 @llvm.read_register.i32(metadata !16)
35 %5 = call i32 @llvm.read_register.i32(metadata !17)
37 %6 = call i32 @llvm.read_register.i32(metadata !18)
39 %7 = call i32 @llvm.read_register.i32(metadata !19)
41 %8 = call i32 @llvm.read_register.i32(metadata !20)
43 %9 = call i32 @llvm.read_register.i32(metadata !21)
[all …]
H A Dspecial-reg.ll8 %reg = call i32 @llvm.read_register.i32(metadata !0)
16 %reg = call i64 @llvm.read_register.i64(metadata !1)
24 %reg = call i32 @llvm.read_register.i32(metadata !2)
32 %reg = call i32 @llvm.read_register.i32(metadata !3)
69 declare i32 @llvm.read_register.i32(metadata) nounwind
70 declare i64 @llvm.read_register.i64(metadata) nounwind
H A Dspecial-reg-acore.ll9 %reg = call i32 @llvm.read_register.i32(metadata !1)
19 %0 = call i32 @llvm.read_register.i32(metadata !0)
20 %1 = call i32 @llvm.read_register.i32(metadata !1)
22 %2 = call i32 @llvm.read_register.i32(metadata !2)
60 declare i32 @llvm.read_register.i32(metadata) nounwind
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dread_register.ll3 declare i32 @llvm.read_register.i32(metadata) #0
4 declare i64 @llvm.read_register.i64(metadata) #0
12 %m0 = call i32 @llvm.read_register.i32(metadata !0)
22 %exec = call i64 @llvm.read_register.i64(metadata !1)
32 %flat_scratch = call i64 @llvm.read_register.i64(metadata !2)
41 %flat_scratch_lo = call i32 @llvm.read_register.i32(metadata !3)
50 %flat_scratch_hi = call i32 @llvm.read_register.i32(metadata !4)
59 %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
68 %exec_hi = call i32 @llvm.read_register.i32(metadata !6)
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/intrinsics/
H A Dnamed-reg-special.ll8 %sp = call i16 @llvm.read_register.i16(metadata !0)
16 %r0 = call i8 @llvm.read_register.i8(metadata !1)
24 %r1 = call i8 @llvm.read_register.i8(metadata !2)
33 %r1r0 = call i16 @llvm.read_register.i16(metadata !1)
37 declare i16 @llvm.read_register.i16(metadata)
38 declare i8 @llvm.read_register.i8(metadata)
H A Dnamed-reg-alloc.ll6 %val1 = call i8 @llvm.read_register.i8(metadata !0)
10 declare i8 @llvm.read_register.i8(metadata)
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/PowerPC/
H A Dread-reg.ll9 %0 = call i64 @llvm.read_register.i64(metadata !0)
11 %1 = call i64 @llvm.read_register.i64(metadata !0)
17 ; CHECK: call i64 @llvm.read_register.i64
18 ; CHECK: call i64 @llvm.read_register.i64
21 declare i64 @llvm.read_register.i64(metadata) #1
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dvlenb.ll11 call i32 @llvm.read_register.i32(metadata !0)
22 %v1 = call i32 @llvm.read_register.i32(metadata !0)
23 %v2 = call i32 @llvm.read_register.i32(metadata !0)
38 %v1 = call i32 @llvm.read_register.i32(metadata !0)
63 %v1 = call i32 @llvm.read_register.i32(metadata !0)
84 %v1 = call i32 @llvm.read_register.i32(metadata !0)
90 declare i32 @llvm.read_register.i32(metadata) nounwind
H A Dget-register-noreserve.ll10 %sp = call i32 @llvm.read_register.i32(metadata !0)
30 %sp = call i32 @llvm.read_register.i32(metadata !1)
40 %sp = call i32 @llvm.read_register.i32(metadata !2)
45 declare i32 @llvm.read_register.i32(metadata) nounwind
H A Dget-register-reserve.ll16 %a1 = call i32 @llvm.read_register.i32(metadata !0)
27 %fp = call i32 @llvm.read_register.i32(metadata !1)
31 declare i32 @llvm.read_register.i32(metadata) nounwind
H A Dget-register-invalid.ll6 %reg = call i32 @llvm.read_register.i32(metadata !0)
10 declare i32 @llvm.read_register.i32(metadata) nounwind
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dnamed-register-n32.ll5 declare i64 @llvm.read_register.i64(metadata)
12 %1 = call i64 @llvm.read_register.i64(metadata !0)
21 %1 = call i64 @llvm.read_register.i64(metadata !1)
H A Dnamed-register-n64.ll5 declare i64 @llvm.read_register.i64(metadata)
12 %1 = call i64 @llvm.read_register.i64(metadata !0)
21 %1 = call i64 @llvm.read_register.i64(metadata !1)
H A Dnamed-register-o32.ll5 declare i32 @llvm.read_register.i32(metadata)
12 %1 = call i32 @llvm.read_register.i32(metadata !0)
21 %1 = call i32 @llvm.read_register.i32(metadata !1)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dframeregister.ll9 %sp = call i64 @llvm.read_register.i64(metadata !0)
10 ; OPT: @llvm.read_register.i64
23 declare i64 @llvm.read_register.i64(metadata) nounwind
H A Dstackpointer.ll9 %sp = call i64 @llvm.read_register.i64(metadata !0)
10 ; OPT: @llvm.read_register.i64
23 declare i64 @llvm.read_register.i64(metadata) nounwind
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dspecial-reg.ll7 %reg = call i64 @llvm.read_register.i64(metadata !0)
15 %reg = call i64 @llvm.read_register.i64(metadata !1)
43 declare i64 @llvm.read_register.i64(metadata) nounwind
H A Dread-pc.ll5 %pc = call i64 @llvm.read_register.i64(metadata !0)
9 declare i64 @llvm.read_register.i64(metadata) nounwind
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dconvergent.ll6 declare i64 @llvm.read_register.i64(metadata) nounwind
37 ; CHECK: call i64 @llvm.read_register.i64(metadata !0) [[$CONVERGENT_ATTR]]
39 %val = call i64 @llvm.read_register.i64(metadata !0) convergent
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dread_register.ll2 …mcpu=bonaire -verify-machineinstrs < %S/../read_register.ll | FileCheck -enable-var-scope %S/../re…
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dzos-stackpointer.ll9 %0 = call i64 @llvm.read_register.i64(metadata !0)
14 declare i64 @llvm.read_register.i64(metadata) nounwind

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