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Searched refs:queues (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/lldb/test/API/macosx/queues/
H A DTestQueues.py21 self.queues()
125 def queues(self): member in TestQueues
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td69 // An instruction can go down one of two issue queues.
73 // Even or an Odd queue. The EXECE represents the even queues and the EXECO
74 // represents the odd queues.
H A DPPCScheduleE500.td20 // queues (GIQx) or Branch issue queue (BIQ).
H A DPPCScheduleE500mc.td20 // queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
H A DPPCScheduleE5500.td21 // queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
H A DPPCScheduleP7.td390 // cycle (from all queues) is 8.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedKryo.td15 // The issue width is set to five, matching the five issue queues for expanded
/llvm-project-15.0.7/lldb/docs/use/
H A Dformatting.rst135 … | The queue name of the thread if the target OS supports dispatch queues
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllvm-mca.rst920 load and store queues respectively. The queues are unbounded by default.
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSchedule.td567 // which describe load/store queues in the LS unit.
/llvm-project-15.0.7/lldb/docs/
H A Dpython_api_enums.rst1221 libdispatch aka Grand Central Dispatch (GCD) queues can be either
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleZnver1.td38 // AGUs feed load store queues @two loads and 1 store per cycle.
H A DX86ScheduleZnver2.td38 // AGUs feed load store queues @two loads and 1 store per cycle.
H A DX86ScheduleZnver3.td91 // The processor uses four decoupled independent integer scheduler queues,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td21 let MicroOpBufferSize = 40; // Issue queues
H A DSystemZScheduleZEC12.td21 let MicroOpBufferSize = 40; // Issue queues
H A DSystemZScheduleZ13.td21 let MicroOpBufferSize = 60; // Issue queues
H A DSystemZScheduleZ16.td21 let MicroOpBufferSize = 60; // Issue queues
H A DSystemZScheduleZ15.td21 let MicroOpBufferSize = 60; // Issue queues
H A DSystemZScheduleZ14.td21 let MicroOpBufferSize = 60; // Issue queues
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUUsage.rst3683 way. An agent can have zero or more AQL queues created for it using an HSA
3689 dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the
5130 * The LDS memory has multiple request queues shared by the SIMDs of a
6393 * The LDS memory has multiple request queues shared by the SIMDs of a
8781 * The LDS memory has multiple request queues shared by the SIMDs of a
11202 * The LDS memory has multiple request queues shared by the SIMDs of a