Home
last modified time | relevance | path

Searched refs:q7 (Results 1 – 25 of 105) sorted by relevance

12345

/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dneon-bitwise-encoding.s117 veor q4, q7, q3
118 veor.8 q4, q7, q3
119 veor.16 q4, q7, q3
120 veor.32 q4, q7, q3
121 veor.64 q4, q7, q3
123 veor.i8 q4, q7, q3
143 veor.f q4, q7, q3
144 veor.d q4, q7, q3
295 vand.s16 q7, q1
301 veor.p16 q7, q1
[all …]
H A Dmve-bitops.s101 vbic q0, q1, q7
105 vbic.s8 q0, q1, q7
109 vbic.s16 q0, q1, q7
113 vbic.s32 q0, q1, q7
117 vbic.u8 q0, q1, q7
121 vbic.u16 q0, q1, q7
129 vbic.i8 q0, q1, q7
177 veor q2, q1, q7
181 veor.s8 q2, q1, q7
193 veor.u8 q2, q1, q7
[all …]
H A Dmve-qdest-qsrc.s49 vqdmladh.s32 q1, q5, q7
223 vmullb.p8 q2, q3, q7
231 vmullt.p8 q1, q1, q7
233 # CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
234 # CHECK-NOFP: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
235 vmullt.p16 q0, q7, q7
243 vmulh.s16 q0, q7, q4
247 vmulh.s32 q0, q7, q4
255 vmulh.u16 q2, q7, q4
307 vqmovnt.u16 q0, q7
[all …]
H A Dmve-float.s102 vcmla.f32 q7, q1, q3, #90
121 vfma.f32 q0, q3, q7
166 vcadd.f32 q2, q5, q7, #0
178 vcvt.f16.s16 q1, q7, #1
202 vcvt.f32.s32 q1, q7, #1
210 vcvt.f32.s32 q1, q7, #6
276 vcvta.s16.f16 q0, q7
284 vcvta.s16.f16 q0, q7
288 vcvtn.u32.f32 q7, q6
292 vcvtp.s32.f32 q0, q7
[all …]
H A Dmve-integer.s60 vmul.i32 q7, q3, q6
213 vdup.16 q7, lr
235 vclz.i8 q0, q7
238 vclz.i16 q4, q7
241 vclz.i32 q7, q5
250 vneg.s32 q7, q2
259 vabs.s32 q0, q7
268 vqneg.s32 q7, q2
300 vmina.s8 q1, q7
308 vmina.s32 q0, q7
[all …]
H A Dneont2-shiftaccum-encoding.s9 vsra.s8 q7, q2, #8
17 vsra.u8 q1, q7, #8
18 vsra.u16 q2, q7, #6
35 vsra.u8 q7, #8
36 vsra.u16 q7, #6
70 @ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x9a,0xff,0x5e,0xe1]
106 vrsra.u16 q7, #16
140 @ CHECK: vrsra.u16 q7, q7, #16 @ encoding: [0x90,0xff,0x5e,0xe3]
150 vsli.16 q2, q7, #15
159 vsri.32 q7, q4, #32
[all …]
H A Dneon-shiftaccum-encoding.s7 vsra.s8 q7, q2, #8
15 vsra.u8 q1, q7, #8
16 vsra.u16 q2, q7, #6
33 vsra.u8 q7, #8
34 vsra.u16 q7, #6
68 @ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x5e,0xe1,0x9a,0xf3]
103 vrsra.u16 q7, #16
137 @ CHECK: vrsra.u16 q7, q7, #16 @ encoding: [0x5e,0xe3,0x90,0xf3]
147 vsli.16 q2, q7, #15
156 vsri.32 q7, q4, #32
[all …]
H A Dneont2-minmax-encoding.s23 vmax.s32 q7, q8, q9
26 vmax.u32 q6, q7, q8
34 vmax.u32 q7, q8
53 @ CHECK: vmax.s32 q7, q8, q9 @ encoding: [0x20,0xef,0xe2,0xe6]
56 @ CHECK: vmax.u32 q6, q7, q8 @ encoding: [0x2e,0xff,0x60,0xc6]
63 @ CHECK: vmax.u32 q7, q7, q8 @ encoding: [0x2e,0xff,0x60,0xe6]
85 vmin.s32 q7, q8, q9
88 vmin.u32 q6, q7, q8
96 vmin.u32 q7, q8
115 @ CHECK: vmin.s32 q7, q8, q9 @ encoding: [0x20,0xef,0xf2,0xe6]
[all …]
H A Dneon-minmax-encoding.s21 vmax.s32 q7, q8, q9
24 vmax.u32 q6, q7, q8
32 vmax.u32 q7, q8
51 @ CHECK: vmax.s32 q7, q8, q9 @ encoding: [0xe2,0xe6,0x20,0xf2]
54 @ CHECK: vmax.u32 q6, q7, q8 @ encoding: [0x60,0xc6,0x2e,0xf3]
61 @ CHECK: vmax.u32 q7, q7, q8 @ encoding: [0x60,0xe6,0x2e,0xf3]
83 vmin.s32 q7, q8, q9
86 vmin.u32 q6, q7, q8
94 vmin.u32 q7, q8
113 @ CHECK: vmin.s32 q7, q8, q9 @ encoding: [0xf2,0xe6,0x20,0xf2]
[all …]
H A Dmve-interleave.s135 vld20.32 {q7, q8}, [r0]
164 # CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
165 vld41.8 {q4, q5, q6, q7}, [r0]!
176 # CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
177 vld43.8 {q4, q5, q6, q7}, [r0]!
194 # CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
195 vld41.16 {q4, q5, q6, q7}, [r0]!
207 vld43.16 {q4, q5, q6, q7}, [r0]!
225 vld41.32 {q4, q5, q6, q7}, [r0]!
237 vld43.32 {q4, q5, q6, q7}, [r0]!
[all …]
H A Dmve-reductions.s109 # CHECK: vmaxav.s32 r10, q7 @ encoding: [0xe8,0xee,0x0e,0xaf]
110 vmaxav.s32 r10, q7
112 # CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
113 vmladav.s16 lr, q0, q7
119 vmladav.u16 lr, q0, q7
128 vmladavx.s16 r0, q0, q7
131 vmladavax.s16 lr, q0, q7
173 vmladav.u8 lr, q1, q7
209 vrmlalvha.u32 lr, r1, q7, q1
225 vmlav.s16 lr, q0, q7
[all …]
H A Dmve-vcmp.s13 # CHECK: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
16 vcmp.f16 ne, q2, q7
54 # CHECK: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
57 vcmp.f32 ge, q0, q7
67 vcmp.f32 gt, q2, q7
116 vcmp.s8 lt, q2, q7
124 vcmp.s8 le, q7, q3
145 vcmp.i16 eq, q4, q7
159 vcmp.s16 ge, q1, q7
167 vcmp.s16 gt, q1, q7
[all …]
H A Dneon-shift-encoding.s125 vsra.s64 q7, #63
142 @ CHECK: vsra.s64 q7, q7, #63 @ encoding: [0xde,0xe1,0x81,0xf2]
161 vsra.u64 q7, #63
178 @ CHECK: vsra.u64 q7, q7, #63 @ encoding: [0xde,0xe1,0x81,0xf3]
197 vsri.64 q7, #63
233 vsli.64 q7, #63
447 vrshl.u32 q7, q10
464 @ CHECK: vrshl.u32 q7, q7, q10 @ encoding: [0xce,0xe5,0x24,0xf3]
483 vshr.u32 q7, #32
500 @ CHECK: vshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe0,0xa0,0xf3]
[all …]
H A Dmve-shifts.s177 vqshrunb.s16 q0, q7, #5
199 vqrshrnb.s16 q0, q7, #8
214 vqrshrnb.s16 q0, q7, #9
263 vshl.u8 q1, q7, q2
279 vqshl.s16 q4, q3, q7
327 vrshl.s16 q1, q4, q7
343 vrshl.u32 q1, q7, q3
503 vshr.s8 q0, q7, #4
506 vshr.s8 q0, q7, #9
524 vshr.u16 q7, q6, #8
[all …]
H A Dmve-minmax.s17 # CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
18 # CHECK-NOFP: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
19 vmin.s8 q3, q0, q7
41 # CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
42 # CHECK-NOFP: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
43 vmax.s8 q3, q0, q7
H A Dneon-sub-encoding.s22 vsub.i64 q4, q7
44 @ CHECK: vsub.i64 q4, q4, q7 @ encoding: [0x4e,0x88,0x38,0xf3]
147 vhsub.u32 q6, q7
160 @ CHECK: vhsub.u32 q6, q6, q7 @ encoding: [0x4e,0xc2,0x2c,0xf3]
164 vsubw.s16 q7, d1
167 vsubw.u16 q7, d1
171 @ CHECK: vsubw.s16 q7, q7, d1 @ encoding: [0x01,0xe3,0x9e,0xf2]
174 @ CHECK: vsubw.u16 q7, q7, d1 @ encoding: [0x01,0xe3,0x9e,0xf3]
H A Dneont2-pairwise-encoding.s21 vpaddl.s8 q4, q7
24 vpaddl.u8 q7, q4
34 @ CHECK: vpaddl.s8 q4, q7 @ encoding: [0xb0,0xff,0x4e,0x82]
37 @ CHECK: vpaddl.u8 q7, q4 @ encoding: [0xb0,0xff,0xc8,0xe2]
51 vpadal.u8 q7, q13
64 @ CHECK: vpadal.u8 q7, q13 @ encoding: [0xb0,0xff,0xea,0xe6]
H A Dneon-add-encoding.s80 vhadd.u32 q6, q7
93 @ CHECK: vhadd.u32 q6, q6, q7 @ encoding: [0x4e,0xc0,0x2c,0xf3]
245 vadd.i16 q7, q1
255 @ CHECK: vadd.i16 q7, q7, q1 @ encoding: [0x42,0xe8,0x1e,0xf2]
261 vaddw.s16 q7, d1
265 vaddw.u16 q7, d1
269 @ CHECK: vaddw.s16 q7, q7, d1 @ encoding: [0x01,0xe1,0x9e,0xf2]
273 @ CHECK: vaddw.u16 q7, q7, d1 @ encoding: [0x01,0xe1,0x9e,0xf3]
H A Dcde-fp-vec.s17 vcx3 p0, q0, q7, q0, #12
81 vcx2a p1, q3, q7, #127
112 vcx3a p1, q3, q7, q6, #15
H A Dcde-vec-pred.s13 vcx2ae p1, q3, q7, #127
17 vcx3at p1, q3, q7, q6, #15
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dthumb-big-stack.ll145 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
147 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
149 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
151 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
153 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
155 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
157 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
159 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
161 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
163 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmve-qdest-qsrc.txt13 # CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
25 # CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
29 # CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
53 # CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
157 # CHECK: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
165 # CHECK: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
169 # CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
177 # CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
181 # CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
241 # CHECK: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
[all …]
H A Dmve-vcmp.txt9 # CHECK: vcmp.f16 ne, q2, q7 @ encoding: [0x35,0xfe,0x8e,0x0f]
37 # CHECK: vcmp.f32 ge, q0, q7 @ encoding: [0x31,0xee,0x0e,0x1f]
45 # CHECK: vcmp.f32 gt, q2, q7 @ encoding: [0x35,0xee,0x0f,0x1f]
65 # CHECK: vcmp.s8 lt, q2, q7 @ encoding: [0x05,0xfe,0x8e,0x1f]
73 # CHECK: vcmp.s8 le, q7, q3 @ encoding: [0x0f,0xfe,0x87,0x1f]
85 # CHECK: vcmp.i16 eq, q4, q7 @ encoding: [0x19,0xfe,0x0e,0x0f]
93 # CHECK: vcmp.s16 ge, q1, q7 @ encoding: [0x13,0xfe,0x0e,0x1f]
101 # CHECK: vcmp.s16 gt, q1, q7 @ encoding: [0x13,0xfe,0x0f,0x1f]
117 # CHECK: vcmp.i32 eq, q2, q7 @ encoding: [0x25,0xfe,0x0e,0x0f]
H A Dmve-integer.txt89 # CHECK: vmul.i32 q7, q3, q6 @ encoding: [0x26,0xef,0x5c,0xe9]
289 # CHECK: vdup.16 q7, lr @ encoding: [0xae,0xee,0x30,0xeb]
319 # CHECK: vclz.i8 q0, q7 @ encoding: [0xb0,0xff,0xce,0x04]
323 # CHECK: vclz.i16 q4, q7 @ encoding: [0xb4,0xff,0xce,0x84]
327 # CHECK: vclz.i32 q7, q5 @ encoding: [0xb8,0xff,0xca,0xe4]
339 # CHECK: vneg.s32 q7, q2 @ encoding: [0xb9,0xff,0xc4,0xe3]
351 # CHECK: vabs.s32 q0, q7 @ encoding: [0xb9,0xff,0x4e,0x03]
363 # CHECK: vqneg.s32 q7, q2 @ encoding: [0xb8,0xff,0xc4,0xe7]
379 # CHECK: vmina.s8 q1, q7 @ encoding: [0x33,0xee,0x8f,0x3e]
387 # CHECK: vmina.s32 q0, q7 @ encoding: [0x3b,0xee,0x8f,0x1e]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dstp-opt-with-renaming.mir292 # CHECK: liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
314 liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
323 # The livein $q7 is killed early, so we can re-use it for renaming.
326 # CHECK: liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
328 # CHECK: renamable $q7 = FADDv2f64 renamable $q7, renamable $q7
329 # CHECK-NEXT: STRQui killed renamable $q7, renamable $x0, 100 :: (store (s128), align 4)
330 # CHECK-NEXT: $q7 = LDRQui $x0, 0 :: (load (s128))
332 # CHECK-NEXT: STPQi killed renamable $q9, killed $q7, renamable $x0, 10 :: (store (s128), align …
349 liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
350 renamable $q7 = FADDv2f64 renamable $q7, renamable $q7
[all …]

12345