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/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vpt-block-elses.mir158 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
164 $q0 = MVE_VORR $q3, $q3, 0, $noreg, $noreg, undef $q0
167 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
173 $q0 = MVE_VORR $q3, $q3, 0, $noreg, $noreg, undef $q0
176 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
185 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
194 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
203 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
211 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
219 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
[all …]
H A Dmve-vpt-3-blocks-kill-vpr.mir70 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
73 …ECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamab…
74 …e $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 2, rena…
76 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
79 …ECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamab…
84 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
85 …renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr…
87 …renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr…
88 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
89 …renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr…
[all …]
H A Dmve-vpt-2-blocks-non-consecutive-ins.mir71 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
74 …ECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamab…
75 …e $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, rena…
77 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
80 …ECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamab…
85 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
86 …renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr…
87 …renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr…
89 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
91 …renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr…
[all …]
H A Dmve-vpt-2-blocks-ctrl-flow.mir71 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
74 …K: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamab…
75 …enamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal renamable $q3, internal renamable $q3, 1, rena…
78 ; CHECK: liveins: $q0, $q1, $q2, $q3, $vpr
81 …K: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamab…
89 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
90 …renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr…
91 …renamable $q1 = nnan ninf nsz MVE_VMINNMf32 renamable $q3, renamable $q3, 1, renamable $vpr, $nore…
94 liveins: $q0, $q1, $q2, $q3, $vpr
96 …renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr…
[all …]
H A Dmve-laneinterleaving.ll191 ; CHECK-NEXT: vand q3, q3, q2
468 ; CHECK-NEXT: vshl.s32 q3, q3, q4
470 ; CHECK-NEXT: vsub.i32 q3, q3, q1
472 ; CHECK-NEXT: vmul.i32 q3, q3, q1
473 ; CHECK-NEXT: vshl.u32 q3, q3, q4
474 ; CHECK-NEXT: vshl.u32 q3, q3, q1
515 ; CHECK-NEXT: vshl.s16 q3, q3, q4
517 ; CHECK-NEXT: vsub.i16 q3, q3, q1
519 ; CHECK-NEXT: vmul.i16 q3, q3, q1
520 ; CHECK-NEXT: vshl.u16 q3, q3, q4
[all …]
H A Dmve-ctpop.ll73 ; CHECK-NEXT: vmov.i8 q3, #0x33
77 ; CHECK-NEXT: vand q0, q0, q3
78 ; CHECK-NEXT: vand q4, q4, q3
101 ; CHECK-NEXT: vmov.i8 q3, #0x33
105 ; CHECK-NEXT: vand q0, q0, q3
106 ; CHECK-NEXT: vand q4, q4, q3
126 ; CHECK-NEXT: vmov.i8 q3, #0x55
128 ; CHECK-NEXT: vand q3, q4, q3
130 ; CHECK-NEXT: vsub.i8 q0, q0, q3
132 ; CHECK-NEXT: vshr.u8 q3, q0, #2
[all …]
H A Dmve-vpt-2-blocks-2-preds.mir70 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
71 …q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, i…
73 … renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed rena…
76 …implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q3, implicit killed $q2…
78 …; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2,…
82 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
83 …renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamab…
85 …renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed …
H A Dmve-vld4.ll51 ; CHECK-NEXT: vadd.i32 q2, q2, q3
78 ; CHECK-NEXT: vadd.i32 q4, q2, q3
86 ; CHECK-NEXT: vadd.i32 q2, q2, q3
119 ; CHECK-NEXT: vadd.i32 q2, q2, q3
128 ; CHECK-NEXT: vadd.i32 q2, q3, q4
140 ; CHECK-NEXT: vadd.i32 q2, q2, q3
261 ; CHECK-NEXT: vmov q3[2], q3[0], r2, r0
264 ; CHECK-NEXT: vmov q3[3], q3[1], r2, r0
268 ; CHECK-NEXT: vmov q3[2], q3[0], r2, r0
277 ; CHECK-NEXT: vmov q3[3], q3[1], r2, r0
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmve-interleave.s24 vld21.8 {q3, q4}, [r0]!
42 vld21.16 {q3, q4}, [r0]!
60 vld21.32 {q3, q4}, [r0]!
78 vst21.8 {q3, q4}, [r0]!
96 vst21.16 {q3, q4}, [r0]!
114 vst21.32 {q3, q4}, [r0]!
150 vld40.8 {q0, q1, q2, q3}, [r0]
162 vld41.8 {q0, q1, q2, q3}, [r0]
168 vld42.8 {q0, q1, q2, q3}, [r0]
174 vld43.8 {q0, q1, q2, q3}, [r0]
[all …]
H A Dneon-bitwise-encoding.s117 veor q4, q7, q3
118 veor.8 q4, q7, q3
119 veor.16 q4, q7, q3
120 veor.32 q4, q7, q3
143 veor.f q4, q7, q3
144 veor.d q4, q7, q3
314 vceq.s16 q5, q3
317 vcgt.s16 q5, q3
320 vcge.s16 q5, q3
336 vacge.f32 q5, q3
[all …]
H A Dmve-qdest-qsrc.s119 # CHECK: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
121 vqrdmlsdh.s8 q3, q3, q0
195 # CHECK: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
196 # CHECK-NOFP: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
197 vmullb.s16 q3, q4, q3
251 vmulh.u8 q3, q5, q2
335 vqmovunb.s16 q0, q3
361 # CHECK: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
362 # CHECK-NOFP: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
363 vmovnt.i32 q3, q3
[all …]
H A Dmve-vpt.s8 vabavt.s32 lr, q1, q3
11 vabave.u8 r12, q1, q3
15 vabav.s16 lr, q1, q3
20 vabavt.s32 lr, q1, q3
21 vabave.s32 lr, q1, q3
22 vabave.s32 lr, q1, q3
23 vabave.s32 lr, q1, q3
28 vabavt.u32 lr, q1, q3
29 vabavt.s32 lr, q1, q3
30 vabavt.s16 lr, q1, q3
[all …]
H A Dmve-vmov-pair.s17 # CHECK: vmov q3[3], q3[1], r4, r1 @ encoding: [0x11,0xec,0x14,0x6f]
18 # CHECK-NOFP: vmov q3[3], q3[1], r4, r1 @ encoding: [0x11,0xec,0x14,0x6f]
19 vmov q3[3], q3[1], r4, r1
22 vmov q4[3], q3[1], r4, r1
25 vmov q3[2], q3[1], r4, r1
H A Dmve-reductions-fp.s7 # CHECK: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
8 # CHECK-NOFP-NOT: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
10 vminnmv.f16 lr, q3
22 # CHECK: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
23 # CHECK-NOFP-NOT: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
25 vminnmav.f32 lr, q3
52 # CHECK: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
53 # CHECK-NOFP-NOT: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
54 # CHECK: vminnmave.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
57 vminnmavt.f32 lr, q3
[all …]
H A Dmve-reductions.s9 vabav.s8 r0, q1, q3
12 vabav.s16 r0, q1, q3
15 vabav.s32 r0, q1, q3
18 vabav.u8 r0, q1, q3
21 vabav.u16 r0, q1, q3
24 vabav.u32 r0, q1, q3
74 vminv.u32 r10, q3
170 vmladav.s8 lr, q3, q0
197 vmlsdav.s16 lr, q0, q3
206 vrmlalvha.s32 lr, r1, q3, q6
[all …]
H A Dmve-bitops.s153 vrev64.16 q1, q3
225 vorn q0, q3, q2
229 vorn.s8 q0, q3, q2
233 vorn.s16 q0, q3, q2
237 vorn.s32 q0, q3, q2
241 vorn.u8 q0, q3, q2
245 vorn.u16 q0, q3, q2
249 vorn.u32 q0, q3, q2
253 vorn.i8 q0, q3, q2
257 vorn.i16 q0, q3, q2
[all …]
H A Dmve-integer.s54 vmul.i8 q0, q0, q3
57 vmul.i16 q6, q0, q3
60 vmul.i32 q7, q3, q6
81 vsub.i8 q3, q2, q5
84 vsub.i16 q0, q3, q6
144 vabd.s32 q2, q3, q2
177 vhsub.s16 q1, q3, q1
198 vhadd.s32 q0, q3, q1
200 # CHECK: vhadd.u8 q3, q0, q3 @ encoding: [0x00,0xff,0x46,0x60]
201 vhadd.u8 q3, q0, q3
[all …]
H A Dmve-float.s21 vrinta.f32 q1, q3
71 vmul.f16 q2, q1, q3
79 vcmla.f16 q3, q2, q1, #0
87 vcmla.f16 q3, q7, q2, #180
94 vcmla.f16 q3, q2, q1, #200
102 vcmla.f32 q7, q1, q3, #90
113 vcmla.f32 q3, q2, q1, #16
117 vfma.f16 q0, q2, q3
121 vfma.f32 q0, q3, q7
137 vadd.f32 q1, q3, q0
[all …]
H A Dmve-qdest-rsrc.s9 vsub.i8 q0, q3, r3
61 vqadd.s16 q3, q4, r2
85 vqdmullb.s32 q0, q3, q7
97 vsub.f16 q0, q3, r7
113 vhsub.s8 q0, q3, lr
317 vfmas.f32 q0, q3, lr
337 vmlas.u16 q0, q3, r12
353 vmla.s8 q0, q3, r8
357 vmla.s16 q1, q3, r10
361 vmla.s32 q1, q3, r1
[all …]
H A Dmve-shifts.s75 vshllt.u16 q0, q3, #16
279 vqshl.s16 q4, q3, q7
335 vrshl.u8 q0, q3, q5
343 vrshl.u32 q1, q7, q3
377 vsli.8 q0, q3, #3
380 vsli.8 q0, q3, #8
387 vsli.16 q0, q3, #16
461 vrshr.s8 q1, q3, #7
464 vrshr.s8 q1, q3, #9
468 vrshr.u8 q1, q3, #2
[all …]
H A Dmve-minmax.s12 # CHECK: vminnm.f16 q3, q0, q1 @ encoding: [0x30,0xff,0x52,0x6f]
13 # CHECK-NOFP-NOT: vminnm.f16 q3, q0, q1 @ encoding: [0x30,0xff,0x52,0x6f]
15 vminnm.f16 q3, q0, q1
17 # CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
18 # CHECK-NOFP: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
19 vmin.s8 q3, q0, q7
41 # CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
42 # CHECK-NOFP: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
43 vmax.s8 q3, q0, q7
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dthumb-big-stack.ll145 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
147 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
149 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
151 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
153 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
155 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
157 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
159 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
161 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
163 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-opt-report/Inputs/
H A Dq3.yaml4 DebugLoc: { File: Inputs/q3.c, Line: 4, Column: 5 }
15 DebugLoc: { File: Inputs/q3.c, Line: 8, Column: 3 }
30 DebugLoc: { File: Inputs/q3.c, Line: 8, Column: 3 }
40 DebugLoc: { File: Inputs/q3.c, Line: 3, Column: 3 }
50 DebugLoc: { File: Inputs/q3.c, Line: 12, Column: 3 }
65 DebugLoc: { File: Inputs/q3.c, Line: 12, Column: 3 }
75 DebugLoc: { File: Inputs/q3.c, Line: 3, Column: 3 }
85 DebugLoc: { File: Inputs/q3.c, Line: 4, Column: 5 }
94 DebugLoc: { File: Inputs/q3.c, Line: 3, Column: 3 }
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmve-interleave.txt25 # CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
49 # CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
73 # CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
97 # CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
121 # CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
145 # CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
149 # CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
153 # CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
165 # CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
173 # CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Doverlapping-copy-bundle.mir7 ; Make sure we don't clobber q3 when we expand the bundle
11 ; CHECK: $q4 = COPY $q3
17 $q4 = COPY $q3
30 ; CHECK: $q4 = COPY $q3
35 $q4 = COPY $q3 {
49 ; CHECK: $q3 = COPY $q2
56 $q3 = COPY $q2

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