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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmve-bitops.s157 vrev64.32 q0, q2
169 vrev16.8 q0, q2
173 vmvn q0, q2
177 veor q2, q1, q7
181 veor.s8 q2, q1, q7
193 veor.u8 q2, q1, q7
205 veor.i8 q2, q1, q7
225 vorn q0, q3, q2
229 vorn.s8 q0, q3, q2
273 vorr q1, q2, q1
[all …]
H A Dvmov-vmvn-replicate.s5 vmov.i64 q2, #0xffffffffffffffff
7 vmov.i32 q2, #0xffffffff
11 vmov.i32 q2, #0xabababab
12 vmov.i16 q2, #0xabab
13 vmov.i16 q2, #0xabab
31 vmov.i32 q2, #0x00a500a5
35 vmov.i32 q2, #0xa500a500
61 vmvn.i32 q2, #0xffffffff
65 vmvn.i32 q2, #0xabababab
67 vmvn.i16 q2, #0xabab
[all …]
H A Dmve-minmax.s23 vmin.s16 q0, q1, q2
27 vmin.s32 q0, q1, q2
31 vmin.u8 q0, q1, q2
35 vmin.u16 q0, q1, q2
39 vmin.u32 q0, q1, q2
47 vmax.s16 q0, q1, q2
51 vmax.s32 q0, q1, q2
55 vmax.u8 q0, q1, q2
59 vmax.u16 q0, q1, q2
63 vmax.u32 q0, q1, q2
[all …]
H A Dmve-integer.s89 # CHECK: vadd.i8 q0, q2, q2 @ encoding: [0x04,0xef,0x44,0x08]
90 vadd.i8 q0, q2, q2
92 # CHECK: vadd.i16 q2, q2, q1 @ encoding: [0x14,0xef,0x42,0x48]
93 vadd.i16 q2, q2, q1
143 # CHECK: vabd.s32 q2, q3, q2 @ encoding: [0x26,0xef,0x44,0x47]
144 vabd.s32 q2, q3, q2
168 vrhadd.u16 q2, q2, q5
226 vcls.s8 q2, q1
250 vneg.s32 q7, q2
256 vabs.s16 q0, q2
[all …]
H A Dmve-interleave.s123 vld20.32 {q0, q2}, [r0]
126 vld20.32 {q0, q1, q2}, [r0]
150 vld40.8 {q0, q1, q2, q3}, [r0]
153 vld40.8 {q0, q1, q2, q3}, [r0]!
156 vld40.8 {q0, q1, q2, q3}, [r11]
162 vld41.8 {q0, q1, q2, q3}, [r0]
168 vld42.8 {q0, q1, q2, q3}, [r0]
171 vld42.8 {q0, q1, q2, q3}, [r0]!
174 vld43.8 {q0, q1, q2, q3}, [r0]
252 vld40.32 {q0, q1, q2}, [r0]
[all …]
H A Dmve-vcmp.s16 vcmp.f16 ne, q2, q7
36 vcmp.f16 le, q2, q6
39 vcmp.f16 hi, q2, q6
42 vcmp.f16 hs, q2, q6
84 # CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
86 vcmp.i8 ne, q2, q2
98 # CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
100 vcmp.s8 ne, q2, q2
106 # CHECK: vcmp.i8 ne, q2, q2 @ encoding: [0x05,0xfe,0x84,0x0f]
108 vcmp.u8 ne, q2, q2
[all …]
H A Dmve-qdest-qsrc.s43 # CHECK: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
44 # CHECK-NOFP: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
45 vqdmladh.s16 q0, q2, q2
79 # CHECK: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
81 vqrdmladh.s32 q0, q2, q2
281 # CHECK: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
283 vrmulh.u32 q1, q2, q2
291 vqmovnt.s16 q2, q0
315 vqmovnt.u32 q0, q2
439 # CHECK: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
[all …]
H A Dmve-shifts.s35 vmovlt.u8 q0, q2
43 vmovlt.u16 q0, q2
47 vshllb.s8 q0, q2, #8
263 vshl.u8 q1, q7, q2
269 # CHECK: vshl.u32 q2, q2, q4 @ encoding: [0x28,0xff,0x44,0x44]
271 vshl.u32 q2, q2, q4
347 vsri.8 q0, q2, #3
350 vsri.8 q0, q2, #9
353 vsri.8 q0, q2, #0
559 vshl.i32 q2, q2, #26
[all …]
H A Dthumb-neon-crypto.s19 sha1c.32 q0, q1, q2
20 @ CHECK: sha1c.32 q0, q1, q2 @ encoding: [0x02,0xef,0x44,0x0c]
21 sha1m.32 q0, q1, q2
22 @ CHECK: sha1m.32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x0c]
23 sha1p.32 q0, q1, q2
24 @ CHECK: sha1p.32 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0c]
25 sha1su0.32 q0, q1, q2
26 @ CHECK: sha1su0.32 q0, q1, q2 @ encoding: [0x32,0xef,0x44,0x0c]
27 sha256h.32 q0, q1, q2
29 sha256h2.32 q0, q1, q2
[all …]
H A Dfullfp16-neon.s5 vadd.f16 q0, q1, q2
12 vsub.f16 q0, q1, q2
19 vmul.f16 q0, q1, q2
33 vmla.f16 q0, q1, q2
47 vmls.f16 q0, q1, q2
61 vfma.f16 q0, q1, q2
68 vfms.f16 q0, q1, q2
75 vceq.f16 q2, q3, q4
82 vceq.f16 q2, q3, #0
89 vcge.f16 q2, q3, q4
[all …]
H A Dmve-float.s41 vrintx.f16 q1, q2
71 vmul.f16 q2, q1, q3
117 vfma.f16 q0, q2, q3
125 vfms.f16 q0, q2, q5
129 vfms.f32 q1, q1, q2
144 vadd.f32 q0, q1, q2
163 vcadd.f32 q2, q2, q3, #270
304 vneg.f32 q0, q2
308 vabs.f16 q0, q2
320 vmaxnma.f32 q2, q6
[all …]
H A Dvorr-vbic-illegal-cases.s5 vorr.i32 q2, #0xffffffff
7 vorr.i32 q2, #0xabababab
8 vorr.i16 q2, #0xabab
9 vorr.i16 q2, #0xabab
18 @ CHECK: vorr.i32 q2, #0xffffffff
30 @ CHECK: vorr.i16 q2, #0xabab
34 @ CHECK: vorr.i16 q2, #0xabab
41 vbic.i16 q2, #0xabab
54 @ CHECK: vbic.i16 q2, #0xabab
61 vbic.i16 q2, #0xf0f0
[all …]
H A Dneon-crypto.s27 sha1c.32 q0, q1, q2
28 sha1m.32 q0, q1, q2
29 sha1p.32 q0, q1, q2
30 sha1su0.32 q0, q1, q2
31 sha256h.32 q0, q1, q2
32 sha256h2.32 q0, q1, q2
33 sha256su1.32 q0, q1, q2
34 @ CHECK: sha1c.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x02,0xf2]
35 @ CHECK: sha1m.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x22,0xf2]
36 @ CHECK: sha1p.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x12,0xf2]
[all …]
H A Darmv8.6a-matmul-error.s9 vsmmla.u8 q0, q1, q2
14 vummla.s8 q0, q1, q2
19 vusmmla.u8 q0, q1, q2
27 vsmmla.s8 d0, q1, q2
32 vummla.u8 q0, d1, q2
47 vusdot.u8 q0, q1, q2
58 vusdot.s8 d0, d1, q2
98 vusdot.s8 q0, q1, q2[0]
H A Dneont2-minmax-encoding.s21 vmax.s8 q1, q2, q3
29 vmax.s8 q2, q3
32 vmax.u8 q11, q2
35 vmax.f32 q2, q1
58 @ CHECK: vmax.s8 q2, q2, q3 @ encoding: [0x04,0xef,0x46,0x46]
64 @ CHECK: vmax.f32 q2, q2, q1 @ encoding: [0x04,0xef,0x42,0x4f]
91 vmin.s8 q2, q3
94 vmin.u8 q11, q2
97 vmin.f32 q2, q1
120 @ CHECK: vmin.s8 q2, q2, q3 @ encoding: [0x04,0xef,0x56,0x46]
[all …]
H A Dneon-minmax-encoding.s19 vmax.s8 q1, q2, q3
27 vmax.s8 q2, q3
30 vmax.u8 q11, q2
33 vmax.f32 q2, q1
56 @ CHECK: vmax.s8 q2, q2, q3 @ encoding: [0x46,0x46,0x04,0xf2]
62 @ CHECK: vmax.f32 q2, q2, q1 @ encoding: [0x42,0x4f,0x04,0xf2]
89 vmin.s8 q2, q3
92 vmin.u8 q11, q2
95 vmin.f32 q2, q1
118 @ CHECK: vmin.s8 q2, q2, q3 @ encoding: [0x56,0x46,0x04,0xf2]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vpt-block-elses.mir70 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
158 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
167 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
176 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
185 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
194 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
203 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
211 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
219 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
226 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
[all …]
H A Dmve-vpt-blocks.ll9 ; CHECK-NEXT: vpt.s32 ge, q0, q2
10 ; CHECK-NEXT: vorrt q0, q1, q2
23 ; CHECK-NEXT: vorrt q3, q1, q2
24 ; CHECK-NEXT: vorrt q0, q3, q2
73 ; CHECK-NEXT: vmove q0, q2
122 ; CHECK-NEXT: vmove q0, q2
123 ; CHECK-NEXT: vmovt q0, q2
139 ; CHECK-NEXT: vmovt q0, q2
140 ; CHECK-NEXT: vmove q0, q2
141 ; CHECK-NEXT: vmovt q0, q2
[all …]
H A Dmve-vpt-block-4-ins.mir39 - { reg: '$q2', virtual-reg: '' }
66 liveins: $q0, $q1, $q2, $q3, $r0
69 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
71 …q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, imp…
73 …ECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamab…
74 …ble $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, re…
75 …; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q…
81 …renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr…
82 …renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr…
83 …renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr…
H A Dmve-vpt-nots.mir57 - { reg: '$q2', virtual-reg: '' }
60 liveins: $q0, $q1, $q2
63 ; CHECK: liveins: $q0, $q1, $q2
86 - { reg: '$q2', virtual-reg: '' }
91 ; CHECK: liveins: $q0, $q1, $q2
106 liveins: $q0, $q1, $q2
113 liveins: $q0, $q1, $q2, $vpr
130 liveins: $q0, $q1, $q2
165 liveins: $q0, $q1, $q2
206 liveins: $q0, $q1, $q2
[all …]
H A Dmve-vpt-block-debug.mir69 - { reg: '$q2', virtual-reg: '' }
72 liveins: $q0, $q1, $q2
75 ; CHECK: liveins: $q0, $q1, $q2
86 …CHECK-NEXT: renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, internal renamable $vpr…
92 …; CHECK-NEXT: $q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, $noreg, undef $q0, debug-location …
98 DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
99 DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
102 …renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renama…
104 DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
106 …renamable $q2 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, …
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dthumb-big-stack.ll145 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
147 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
149 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
151 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
153 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
155 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
157 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
159 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
161 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
163 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
[all …]
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv60-vcmp.s5 #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) }
6 q2|=vcmp.eq(v17.b,v1.b)
9 q2&=vcmp.gt(v27.uw,v4.uw)
12 q2&=vcmp.gt(v24.uh,v12.uh)
18 q2&=vcmp.gt(v13.w,v26.w)
21 q2&=vcmp.gt(v5.h,v13.h)
30 q2&=vcmp.eq(v2.h,v3.h)
51 q2^=vcmp.eq(v15.w,v2.w)
75 q2|=vcmp.gt(v16.ub,v0.ub)
78 q2|=vcmp.gt(v23.w,v17.w)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dbitwise-pred-128b.ll8 %q2 = and <128 x i1> %q0, %q1
9 %v0 = zext <128 x i1> %q2 to <128 x i8>
20 %q2 = or <128 x i1> %q0, %q1
21 %v0 = zext <128 x i1> %q2 to <128 x i8>
30 %q2 = xor <128 x i1> %q0, %q1
40 %q2 = and <64 x i1> %q0, %q1
50 %q2 = or <64 x i1> %q0, %q1
60 %q2 = xor <64 x i1> %q0, %q1
70 %q2 = and <32 x i1> %q0, %q1
80 %q2 = or <32 x i1> %q0, %q1
[all …]
H A Dbitwise-pred-64b.ll8 %q2 = and <64 x i1> %q0, %q1
9 %v0 = zext <64 x i1> %q2 to <64 x i8>
18 %q2 = or <64 x i1> %q0, %q1
19 %v0 = zext <64 x i1> %q2 to <64 x i8>
28 %q2 = xor <64 x i1> %q0, %q1
38 %q2 = and <32 x i1> %q0, %q1
48 %q2 = or <32 x i1> %q0, %q1
58 %q2 = xor <32 x i1> %q0, %q1
68 %q2 = and <16 x i1> %q0, %q1
78 %q2 = or <16 x i1> %q0, %q1
[all …]

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