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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dprefer-avx256-trunc.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+prefer-256-bit | FileCheck %s --c…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,-prefer-256-bit | FileCheck %s --c…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+prefer-256-bit | FileCheck %s --ch…
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,-prefer-256-bit | FileCheck %s --ch…
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+prefer-256-bit | FileCheck %s --c…
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,-prefer-256-bit | FileCheck %s --c…
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+prefer-256-bit | FileCh…
9 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,-prefer-256-bit | FileCh…
H A Dprefer-avx256-mask-shuffle.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+prefer-256-bit | FileCheck %s --c…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,-prefer-256-bit | FileCheck %s --c…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+prefer-256-bit | FileCh…
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,-prefer-256-bit | FileCh…
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+prefer-256-bit | FileCheck %s --ch…
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,-prefer-256-bit | FileCheck %s --ch…
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+prefer-256-bit | FileCheck %s --c…
9 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,-prefer-256-bit | FileCheck %s --c…
H A Dprefer-avx256-wide-mul.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512bw,+prefer-256-bit | FileCh…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512bw,-prefer-256-bit | FileCh…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+prefer-256-bit | FileCheck %s --c…
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,-prefer-256-bit | FileCheck %s --c…
H A Dprefer-avx256-popcnt.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512vpopcntdq,+prefer-256-bit |…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512vpopcntdq,-prefer-256-bit |…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vpopcntdq,+prefer-256-bit | …
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vpopcntdq,-prefer-256-bit | …
H A Dprefer-avx256-lzcnt.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512cd,+prefer-256-bit | FileCh…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512cd,-prefer-256-bit | FileCh…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512cd,+prefer-256-bit | FileChe…
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512cd,-prefer-256-bit | FileChe…
H A Dmusttail-fastcall.ll114 define i32 @call_vector_thunk_prefer256() "min-legal-vector-width"="256" "prefer-vector-width"="256…
119 define x86_vectorcallcc i32 @vector_thunk_prefer256(...) "min-legal-vector-width"="256" "prefer-vec…
193 …r256(i32 inreg %a, i32 inreg %b, i32 %c) "min-legal-vector-width"="256" "prefer-vector-width"="256…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-movi.ll124 ; FIXME: prefer "mov x0, #-16639; lsl x0, x0, #24"
135 ; FIXME: prefer "mov w0, #-63; movk x0, #17, lsl #32"
325 ; FIXME: prefer "mov x0, #2147483646; orr x0, x0, #36028659580010496"
354 ; FIXME: prefer "mov x0, #72340172838076673; and x0, x0, #2199023255296"
365 ; FIXME: prefer "mov w0, #-1431655766; movk x0, #9, lsl #32"
376 ; FIXME: prefer "mov w0, #-13690; orr x0, x0, #0x1111111111111111"
387 ; FIXME: prefer "mov w0, #-305397761; eor x0, x0, #0x3333333333333333"
398 ; FIXME: prefer "mov x0, #536866816; orr x0, x0, #0x3fff800000000000"
409 ; FIXME: prefer "mov x0, #558551907040256; orr x0, x0, #0x1000100010001000"
420 ; FIXME: prefer "mov x0, #281479271743489; orr x0, x0, #0x1000100010001000"
[all …]
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/
H A Dprefer-member-initializer.rst1 .. title:: clang-tidy - cppcoreguidelines-prefer-member-initializer
3 cppcoreguidelines-prefer-member-initializer
12 …github.com/isocpp/CppCoreGuidelines/blob/master/CppCoreGuidelines.md#c49-prefer-initialization-to-…
20 …github.com/isocpp/CppCoreGuidelines/blob/master/CppCoreGuidelines.md#c48-prefer-in-class-initializ…
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Davx512.ll2 ; RUN: opt -mattr=+avx512vl,+prefer-256-bit --loop-vectorize -S < %s | llc -mattr=+avx512f | FileCh…
46 ; Verify that the "prefer-vector-width=256" attribute prevents the use of 512-bit
57 define void @g(i32* %a, i32 %n) "prefer-vector-width"="256" {
81 ; Verify that the "prefer-vector-width=512" attribute override the subtarget
96 define void @h(i32* %a, i32 %n) "prefer-vector-width"="512" {
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/llvm/
H A Dprefer-register-over-unsigned.rst1 .. title:: clang-tidy - llvm-prefer-register-over-unsigned
3 llvm-prefer-register-over-unsigned
H A Dprefer-isa-or-dyn-cast-in-conditionals.rst1 .. title:: clang-tidy - llvm-prefer-isa-or-dyn-cast-in-conditionals
3 llvm-prefer-isa-or-dyn-cast-in-conditionals
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/google/
H A Dobjc-avoid-throwing-exception.rst8 For the same reason as the Google C++ style guide, we prefer not throwing
14 Instead, prefer passing in ``NSError **`` and return ``BOOL`` to indicate success or failure.
/llvm-project-15.0.7/lldb/test/Shell/Unwind/
H A Dprefer-debug-over-eh-frame.test1 # Test that we prefer debug_frame over eh_frame unwind plans. They usually
11 # RUN: %clang_host -g %p/Inputs/call-asm.c %p/Inputs/prefer-debug-over-eh-frame.s -o %t
/llvm-project-15.0.7/llvm/utils/lit/lit/llvm/
H A Dconfig.py567 def prefer(this, to): function
571 (' clang ', prefer('%clang', 'clang')))
573 (r' clang\+\+ ', prefer('%clangxx', 'clang++')))
575 (' clang-cc ', prefer('%clang_cc1', 'clang-cc')))
577 (' clang-cl ', prefer('%clang_cl', 'clang-cl')))
580 prefer('%clang_analyze_cc1', 'clang -cc1 -analyze')))
582 (' clang -cc1 ', prefer('%clang_cc1', 'clang -cc1')))
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-strict-fadd-cost.ll3 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -force-vector-width=4 -force-vector-interl…
6 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -force-vector-width=8 -force-vector-interl…
9 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -force-vector-width=4 -force-vector-interl…
H A Dscalarize-store-with-predication.ll2 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -S -o - < %s | FileCheck %s
4 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -S -o - < %s | FileCheck %s
/llvm-project-15.0.7/clang-tools-extra/clangd/index/
H A DMerge.cpp192 static bool prefer(const SymbolLocation &L, const SymbolLocation &R) { in prefer() function
221 if (prefer(O.CanonicalDeclaration, S.CanonicalDeclaration)) in mergeSymbol()
223 if (prefer(O.Definition, S.Definition)) in mergeSymbol()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dgep-sext.ll7 ; We prefer to canonicalize the machine width gep indices early
28 ; If we can use a zext, we prefer that. This requires
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-const-04.ll78 ; Check the next halfword up, which is out of range. We prefer STHY
90 ; Check negative displacements, for which we again prefer STHY.
H A Dint-const-05.ll69 ; Check the next word up, which is out of range. We prefer STY in that case.
80 ; Check negative displacements, for which we again prefer STY.
H A Dint-const-06.ll69 ; Check the next doubleword up, which is out of range. We prefer STG
81 ; Check negative displacements, for which we again prefer STG.
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dlsr-insns-2.ll6 ; For x86 LSR should prefer complicated address to new lsr induction
21 ; LSR should prefer complicated address to additonal add instructions.
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/
H A Dmin-legal-vector-width.ll758 …nd uwtable "target-features"="+avx512vl" "min-legal-vector-width"="512" "prefer-vector-width"="512…
759 …nd uwtable "target-features"="+avx512vl" "min-legal-vector-width"="512" "prefer-vector-width"="256…
760 …nd uwtable "target-features"="+avx512vl" "min-legal-vector-width"="256" "prefer-vector-width"="256…
761 …unwind uwtable "target-features"="+avx2" "min-legal-vector-width"="512" "prefer-vector-width"="256…
762 …unwind uwtable "target-features"="+avx2" "min-legal-vector-width"="256" "prefer-vector-width"="256…
768 …curse nosync nounwind willreturn uwtable "min-legal-vector-width"="512" "prefer-vector-width"="256…
769 …curse nosync nounwind willreturn uwtable "min-legal-vector-width"="256" "prefer-vector-width"="256…
777 …curse nosync nounwind willreturn uwtable "min-legal-vector-width"="512" "prefer-vector-width"="256…
785 …curse nosync nounwind willreturn uwtable "min-legal-vector-width"="512" "prefer-vector-width"="256…
786 …curse nosync nounwind willreturn uwtable "min-legal-vector-width"="256" "prefer-vector-width"="256…
[all …]
/llvm-project-15.0.7/mlir/utils/vim/
H A DREADME9 prefer, create symlinks to the files here.
/llvm-project-15.0.7/llvm/test/Transforms/Inline/
H A Dalways-inline-attr.ll41 …th"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "prefer-vector-width"="128…
42 …th"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "prefer-vector-width"="128…

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