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/llvm-project-15.0.7/flang/test/Semantics/
H A Devent01.f9019 event post(concert)
20 event post(concert[1])
21 event post(occurrences(1))
22 event post(occurrences(1)[1])
32 event post(non_event)
35 event post(non_coarray)
38 event post(occurrences)
41 event post(occurrences[1])
45 event post(event=concert)
61 event post(concert, stat)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Darm-eabi.ll1 ; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EA…
2 ; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-…
3 ; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=C…
4 ; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK…
5 ; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHE…
6 ; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHEC…
7 ; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CH…
8 ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-pref…
15 ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix…
16 ; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-pref…
[all …]
H A D2014-07-18-earlyclobber-str-post.ll6 define i32* @earlyclobber-str-post(i32* %addr) nounwind {
7 ; CHECK-LABEL: earlyclobber-str-post
15 define i16* @earlyclobber-strh-post(i16* %addr) nounwind {
16 ; CHECK-LABEL: earlyclobber-strh-post
25 define i8* @earlyclobber-strb-post(i8* %addr) nounwind {
26 ; CHECK-LABEL: earlyclobber-strb-post
H A Dpostrasched.ll2 ; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -debug-only=machine-scheduler,post-RA-sched -print…
5 ; Pre and post ra machine scheduling
21 ; CHECK: Subtarget disables post-MI-sched.
/llvm-project-15.0.7/lldb/examples/test/
H A Dusage-pre-post-flight2 # The following examples first show a bad pre/post flight config file followed by a good pre/post c…
5 …ldb/svn/ToT/test $ ./dotest.py -A x86_64 -v -c ../examples/test/.lldb-pre-post-flight.bad functio…
8 …ldb/svn/ToT/test $ ./dotest.py -A x86_64 -v -c ../examples/test/.lldb-pre-post-flight functionali…
33 print "\nRunning post-flight function:"
38 Command invoked: python ./dotest.py -A x86_64 -v -c ../examples/test/.lldb-pre-post-flight function…
50 Running post-flight function:
58 Running post-flight function:
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/pipeliner/
H A Dswp-phi-start.mir8 # CHECK: intregs = S2_addasl_rrri %{{[0-9]+}}, %{{[0-9]+}}, 1, post-instr-symbol <mcsymbol Stage…
9 # CHECK: intregs = L2_loadruh_io %{{[0-9]+}}, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :…
10 # CHECK: intregs = S2_storerh_pi %{{[0-9]+}}, -2, %{{[0-9]+}}, post-instr-symbol <mcsymbol Stage…
11 # CHECK: intregs = nsw A2_addi %{{[0-9]+}}, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
138 %1:intregs = PHI %7, %bb.2, %5, %bb.3, post-instr-symbol <mcsymbol Stage-3_Cycle-0>
139 %2:intregs = PHI %10, %bb.2, %4, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
140 %3:intregs = PHI %6, %bb.2, %2, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
141 %11:intregs = S2_addasl_rrri %7, %3, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
142 …%12:intregs = L2_loadruh_io %11, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load (s16) f…
143 …%5:intregs = S2_storerh_pi %1, -2, %12, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (store (s1…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LCSSA/
H A Dbasictest.ll9 loop.interior: ; preds = %post.if, %entry
13 br label %post.if
16 br label %post.if
17 post.if: ; preds = %if.false, %if.true
20 loop.exit: ; preds = %post.if
H A DDontInsertDebugValuesForPHIs.ll12 loop.interior: ; preds = %post.if, %entry
17 br label %post.if
21 br label %post.if
23 post.if: ; preds = %if.false, %if.true
30 loop.exit: ; preds = %post.if
/llvm-project-15.0.7/mlir/test/IR/
H A Dvisitors.mlir49 // CHECK-LABEL: Op post-order visits
60 // CHECK-LABEL: Block post-order visits
67 // CHECK-LABEL: Region post-order visits
81 // CHECK-LABEL: Op post-order erasures (skip)
90 // CHECK-LABEL: Block post-order erasures (skip)
95 // CHECK-LABEL: Op post-order erasures (no skip)
152 // CHECK-LABEL: Op post-order visits
163 // CHECK-LABEL: Block post-order visits
170 // CHECK-LABEL: Region post-order visits
184 // CHECK-LABEL: Op post-order erasures (skip)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsendmsg-m0-hazard.mir1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
2 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | F…
3 # RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
4 # RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
H A Dgws-hazards.mir2 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
3 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | F…
4 # RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
5 # RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
6 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - …
7 # RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - …
H A Dpost-ra-sched-reset.mir1 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=post-RA-sched -verify-machineinstrs -debug-only=pos…
H A Dhazard-in-bundle.mir1 # RUN: llc -march=amdgcn -mcpu=gfx902 -mattr=+xnack -verify-machineinstrs -run-pass post-RA-hazard…
2 # RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -run-pass post-RA-hazard…
3 …-wavefrontsize32,+wavefrontsize64,-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o…
H A Dhazard-buffer-store-v-interp.mir1 # RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | F…
2 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | …
H A Dhazard-hidden-bundle.mir1 # RUN: llc -march=amdgcn -mcpu=gfx902 -mattr=+xnack -verify-machineinstrs -run-pass post-RA-hazard…
2 # RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -run-pass post-RA-hazard…
3 …-wavefrontsize32,+wavefrontsize64,-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o…
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dtwo-entry-phi-return.ll43 %cmp = phi i1 [ true, %pre.for ], [ false, %post.for ]
44 %storemerge = phi i32 [ 0, %pre.for ], [ 1, %post.for ]
46 br i1 %cmp, label %post.for, label %pre.for
48 post.for:
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td28 // Pseudo for a rev16 instruction. Produced post-legalization from
36 // Pseudo for a rev32 instruction. Produced post-legalization from
44 // Pseudo for a rev64 instruction. Produced post-legalization from
52 // Represents an uzp1 instruction. Produced post-legalization from
60 // Represents an uzp2 instruction. Produced post-legalization from
68 // Represents a zip1 instruction. Produced post-legalization from
76 // Represents a zip2 instruction. Produced post-legalization from
84 // Represents a dup instruction. Produced post-legalization from
114 // Represents a trn1 instruction. Produced post-legalization from
122 // Represents a trn2 instruction. Produced post-legalization from
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/X86/
H A Dinstr-symbols-and-mcsymbol-operands.mir2 # This test ensures that the MIR parser parses pre- and post-instruction symbols
48 … $rsp, implicit $ssp, implicit $edi, pre-instr-symbol <mcsymbol .Lpre_f>, post-instr-symbol <mcsym…
49 …; CHECK: CALL64pcrel32 @f, {{.*}}, pre-instr-symbol <mcsymbol .Lpre_f>, post-instr-symbol <mcsymbo…
62 …CALL64pcrel32 @h, csr_64, implicit $rsp, implicit $ssp, implicit $edi, post-instr-symbol <mcsymbol…
63 ; CHECK: CALL64pcrel32 @h, {{.*}}, post-instr-symbol <mcsymbol .Lpost_h>, debug-location
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dthinlto_embed_bitcode.ll3 ; check the -lto-embed-bitcode=post-thinlto-merge does not perform optimizations
16 ; For the post-merge case, perform the embedded bitcode extraction, then
18 …o %t.o -x ir %t1.bc -c -fthinlto-index=%t.o.thinlto.bc -mllvm -lto-embed-bitcode=post-merge-pre-opt
24 ; We should only need the index and the post-thinlto merged module to generate
27 …-embedded.bc -c -fthinlto-index=%t.o.thinlto.bc -mllvm -lto-embed-bitcode=post-merge-pre-opt -mllv…
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Dtrunc_multi_uses.ll13 ;; These tests check cases where expression dag post-dominated by TruncInst
31 ; make sure zext have another use that is not post-dominated by the TruncInst.
50 ; make sure zext have another use that is not post-dominated by the TruncInst.
69 ; make sure zext have another use that is not post-dominated by the TruncInst.
88 ; make sure zext have another use that is not post-dominated by the TruncInst.
110 ; make sure zext have another use that is not post-dominated by the TruncInst.
130 ; make sure zext have another use that is not post-dominated by the TruncInst.
149 ; make sure zext have another use that is not post-dominated by the TruncInst.
168 ; make sure zext have another use that is not post-dominated by the TruncInst.
187 ; make sure zext have another use that is not post-dominated by the TruncInst.
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dtestb-je-fusion.ll2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=0 | FileChec…
3 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=0 | FileChec…
4 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=0 | FileChec…
5 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=1 | FileChec…
6 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=1 | FileChec…
7 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=1 | FileChec…
8 …tr=-macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck…
9 …tr=-macrofusion,+branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck…
10 …tr=+macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck…
H A Dinstr-symbols.mir3 # Test the emission of pre- and post-instruction labels.
36 … $rsp, implicit $ssp, implicit $edi, pre-instr-symbol <mcsymbol .Lpre_f>, post-instr-symbol <mcsym…
53 …CALL64pcrel32 @h, csr_64, implicit $rsp, implicit $ssp, implicit $edi, post-instr-symbol <mcsymbol…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dldst-opt.ll677 ; CHECK-LABEL: load-post-indexed-byte
725 ; CHECK-LABEL: load-post-indexed-word
797 ; CHECK-LABEL: load-post-indexed-float
821 ; CHECK-LABEL: load-post-indexed-double
855 ; CHECK-LABEL: store-post-indexed-byte
901 ; CHECK-LABEL: store-post-indexed-word
970 ; CHECK-LABEL: store-post-indexed-float
993 ; CHECK-LABEL: store-post-indexed-double
1118 ; CHECK-LABEL: post-indexed-sub-word
1190 ; CHECK-LABEL: post-indexed-sub-float
[all …]
H A Dglobal-merge-3.ll1 …linux-gnu -aarch64-enable-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck…
2 …ux-gnuabi -aarch64-enable-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck…
3 …apple-ios -aarch64-enable-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck…
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Danti-dep-partial.mir1 # RUN: llc -march=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s

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