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/llvm-project-15.0.7/lld/test/ELF/
H A Dppc64-got-to-pcrel-relaxation.s34 # CHECK-D-NEXT: pld 8
35 # CHECK-D-NEXT: pld 9
40 # CHECK-D-NEXT: pld 10
67 # CHECK-D-NEXT: pld 9
70 # CHECK-D-NEXT: pld 9
92 # CHECK-D-NEXT: pld 9
94 # CHECK-D-NEXT: pld 9
116 # CHECK-D-NEXT: pld 9
118 # CHECK-D-NEXT: pld 9
140 # CHECK-D-NEXT: pld 9
[all …]
H A Dppc64-tls-pcrel-ie.s64 # IE-NEXT: pld 3, 12512(0), 1
73 pld 3, x@got@tprel@pcrel(0), 1
87 pld 3, x@got@tprel@pcrel(0), 1
92 # IE-NEXT: pld 3, 8416(0), 1
101 pld 3, x@got@tprel@pcrel(0), 1
106 # IE-NEXT: pld 3, 4320(0), 1
107 # IE-NEXT: pld 4, 4320(0), 1
119 pld 3, x@got@tprel@pcrel(0), 1
120 pld 4, y@got@tprel@pcrel(0), 1
126 # IE-NEXT: pld 4, 232(0), 1
[all …]
H A Dppc64-reloc-got-pcrel34.s22 # CHECK-NEXT: pld 3, 458936(0), 1
29 pld 3, glob_int@got@PCREL(0), 1
34 # CHECK-NEXT: pld 3, 458928(0), 1
39 pld 3, glob_int8@got@PCREL(0), 1
44 # CHECK-NEXT: pld 3, 200(0), 1
56 pld 3, glob_int8_big@got@PCREL(0), 1
H A Dppc64-check-missing-tocbase.s20 # INPUT-ASM: pld 3, 0(0), 1
34 pld 3, glob_int@got@pcrel(0), 1
/llvm-project-15.0.7/llvm/test/MC/PowerPC/
H A Dppc64-reloc-directive-pcrel.s18 pld 3, vec@got@pcrel(0), 1
26 # CHECK: pld 3, 0(0), 1
37 pld 3, vec@got@pcrel(0), 1
59 pld 3, vec@got@pcrel(0), 1
89 pld 3, vec@got@pcrel(0), 1
120 pld 3, vec@got@pcrel(0), 1
155 pld 3, vec@got@pcrel(0), 1
177 pld 3, vec@got@pcrel(0), 1
197 pld 3, vec@got@pcrel(0), 1
218 pld 3, vec@got@pcrel(0), 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dpcrel-got-indirect.ll25 ; LE-NEXT: pld r3, valChar@got@pcrel(0), 1
33 ; BE-NEXT: pld r3, valChar@got@pcrel(0), 1
47 ; LE-NEXT: pld r3, valChar@got@pcrel(0), 1
54 ; BE-NEXT: pld r3, valChar@got@pcrel(0), 1
107 ; LE-NEXT: pld r3, valInt@got@pcrel(0), 1
115 ; BE-NEXT: pld r3, valInt@got@pcrel(0), 1
128 ; LE-NEXT: pld r3, valInt@got@pcrel(0), 1
228 ; LE-NEXT: pld r3, ptr@got@pcrel(0), 1
236 ; BE-NEXT: pld r3, ptr@got@pcrel(0), 1
249 ; LE-NEXT: pld r3, ptr@got@pcrel(0), 1
[all …]
H A Dpcrel-linkeropt.ll40 ; which is defined between the pld and the stb.
43 ; CHECK-NEXT: pld r3, input8@got@pcrel(0), 1
45 ; CHECK-NEXT: pld r4, output8@got@pcrel(0), 1
59 ; which is defined between the pld and the sth.
62 ; CHECK-NEXT: pld r3, input16@got@pcrel(0), 1
64 ; CHECK-NEXT: pld r4, output16@got@pcrel(0), 1
78 ; CHECK-NEXT: pld r3, input32@got@pcrel(0), 1
80 ; CHECK-NEXT: pld r4, output32@got@pcrel(0), 1
94 ; CHECK-NEXT: pld r3, input64@got@pcrel(0), 1
96 ; CHECK-NEXT: pld r4, output64@got@pcrel(0), 1
[all …]
H A Dpcrel-tls-initial-exec.ll19 ; CHECK-S-NEXT: pld r3, x@got@tprel@pcrel(0), 1
23 ; CHECK-O: 00 00 10 04 00 00 60 e4 pld 3, 0(0), 1
35 ; CHECK-S-NEXT: pld r3, x@got@tprel@pcrel(0), 1
39 ; CHECK-O: 00 00 10 04 00 00 60 e4 pld 3, 0(0), 1
H A DLQ-STQ-32bit-offset.ll17 ; CHECK-NEXT: pld r3, s1@PCREL+8(0), 1
19 ; CHECK-NEXT: pld r3, s1@PCREL(0), 1
50 ; CHECK-NEXT: pld r3, s1@PCREL+8(0), 1
52 ; CHECK-NEXT: pld r3, s1@PCREL(0), 1
H A Dpcrel-linkeropt-option.ll17 ; DEFAULT-NEXT: pld r3, input8@got@pcrel(0), 1
25 ; ON-NEXT: pld r3, input8@got@pcrel(0), 1
33 ; OFF-NEXT: pld r3, input8@got@pcrel(0), 1
H A Dpcrel-relocation-plus-offset.ll52 ; CHECK-S-NEXT: pld r3, array1@got@pcrel(0), 1
58 ; CHECK-O: pld 3, 0(0), 1
71 ; CHECK-S-NEXT: pld r3, array1@got@pcrel(0), 1
77 ; CHECK-O: pld 3, 0(0), 1
H A Dpcrel.ll44 ; CHECK-S-NEXT: pld r3, valIntGlob@got@pcrel(0), 1
51 ; CHECK-O: pld 3, 0(0), 1
H A Dpcrel-tail-calls.ll22 ; CHECK-NEXT: pld r3, Func@got@pcrel(0), 1
23 ; CHECK-NEXT: pld r4, Function@got@pcrel(0), 1
38 ; CHECK-NEXT: pld r12, FuncLocal@PCREL(0), 1
51 ; CHECK-NEXT: pld r3, Func@got@pcrel(0), 1
H A Dglobal-address-non-got-indirect-access.ll106 ; CHECK-NEXT: pld r3, _ZL19StaticSignedLongVar@PCREL(0), 1
149 ; CHECK-NEXT: pld r3, _ZL23StaticSigned__Int128Var@PCREL(0), 1
150 ; CHECK-NEXT: pld r4, _ZL23StaticSigned__Int128Var@PCREL+8(0), 1
448 ; CHECK-NEXT: pld r3, _ZL3ptr@PCREL(0), 1
464 ; CHECK-NEXT: pld r3, str@PCREL(0), 1
476 ; CHECK-NEXT: pld r3, str@PCREL(0), 1
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dprefetch.ll8 ; CHECK-T1-NOT: pld
14 ; ARM: pld [r0]
18 ; ARM-MP: pld [r0]
22 ; THUMB2: pld [r0]
31 ; ARM: pld [r0, #1023]
47 ; THUMB2: pld [r0, r1]
85 ;ARM: pld [sp]
86 ;ARM: pld [sp, #50]
87 ;ARM: pld [sp, #-50]
90 ;THUMB2: pld [sp]
[all …]
H A D2009-07-09-asm-p-constraint.ll5 call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(i8* %x) nounwind
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Darm-shift-encoding.s23 pld [r0, r0]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
26 pld [r0, r0, lsl #0]
27 pld [r0, r0, lsl #16]
28 pld [r0, r0, asr #32]
29 pld [r0, r0, asr #16]
30 pld [r0, r0, rrx]
31 pld [r0, r0, ror #16]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumb2-preloads.txt11 # V6T2: pld [r1, #3]
14 # V6T2: pld [r2, #-5]
27 # V6T2: pld [pc, #8]
30 # V6T2: pld [pc, #-5]
33 # V6T2: pld [r5, r6]
36 # V6T2: pld [r7, r8, lsl #1]
/llvm-project-15.0.7/libc/AOR_v20.02/string/arm/
H A Dstrlen-armv6t2.S45 pld [srcin, #0]
50 pld [src, #32]
57 pld [src, #64]
114 pld [src, #64]
H A Dmemcpy.S431 pld [src, #8]
432 pld [src, #72]
434 pld [src, #136]
441 pld [src, #200]
446 pld [src, #232]
483 pld [src]
484 pld [src, #64]
489 pld [src, #(2 * 64)]
501 pld [src, #(3 * 64)]
505 pld [src, #(4 * 64)]
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/PowerPC/
H A Dmcpu.s9 # FUTURE-NEXT: pld 3, 0(0), 1
15 pld 3, 0(0), 1
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/ARM/
H A Dliteral-thumb2.s42 pld bar
48 @ CHECK-NEXT: 30: pld [pc, #96] @ 0x94 <bar>
57 pld bar
63 @ CHECK-NEXT: 4a: pld [pc, #72] @ 0x94 <bar>
H A Dliteral-arm.s23 pld bar
27 @ CHECK-NEXT: 14: pld [pc, #40] @ 0x44 <bar>
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dx87.ll8 define void @test(i32 %i, i64 %l, ptr %pf, ptr %pd, ptr %pld) nounwind readnone {
55 store fp128 %tmp8, ptr %pld
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dcortex-a57-thumb.s448 pld [r5, #-4]
449 pld [r6, #32]
450 pld [r6, #33]
451 pld [r6, #257]
452 pld [r7, #257]
453 pld [r8, r1]
454 pld [r5, r2]
458 pld [sp, r2]
459 pld [pc, #-0]
460 pld [pc, #455]
[all …]

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