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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-dyn-stackalloc.mir38 %1:_(p5) = G_DYN_STACKALLOC %0, 1
72 %1:_(p5) = G_DYN_STACKALLOC %0, 2
106 %1:_(p5) = G_DYN_STACKALLOC %0, 4
140 %1:_(p5) = G_DYN_STACKALLOC %0, 8
174 %1:_(p5) = G_DYN_STACKALLOC %0, 16
212 %1:_(p5) = G_DYN_STACKALLOC %0, 32
250 %1:_(p5) = G_DYN_STACKALLOC %0, 64
317 %1:_(p5) = G_DYN_STACKALLOC %0, 4
351 %1:_(p5) = G_DYN_STACKALLOC %0, 8
385 %1:_(p5) = G_DYN_STACKALLOC %0, 16
[all …]
H A Dlegalize-load-private.mir4269 ; SI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
4275 ; CI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
4281 ; VI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
4287 ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
4293 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
4299 ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
4302 %1:_(p5) = G_LOAD %0 :: (load (p5), align 4, addrspace 5)
4381 ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), align 2, addrspace 5)
4384 %1:_(p5) = G_LOAD %0 :: (load (p5), align 2, addrspace 5)
4513 ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), align 1, addrspace 5)
[all …]
H A Dlegalize-insert-vector-elt.mir432 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p5) = COPY [[PTR_ADD3]](p5)
436 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p5) = COPY [[PTR_ADD4]](p5)
440 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p5) = COPY [[PTR_ADD5]](p5)
444 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(p5) = COPY [[PTR_ADD6]](p5)
448 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(p5) = COPY [[PTR_ADD7]](p5)
452 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(p5) = COPY [[PTR_ADD8]](p5)
456 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p5) = COPY [[PTR_ADD9]](p5)
460 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p5) = COPY [[PTR_ADD10]](p5)
464 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p5) = COPY [[PTR_ADD11]](p5)
468 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p5) = COPY [[PTR_ADD12]](p5)
[all …]
H A Dlegalize-sextload-private.mir14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
17 %0:_(p5) = COPY $vgpr0
31 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
34 %0:_(p5) = COPY $vgpr0
47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
50 %0:_(p5) = COPY $vgpr0
64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
68 %0:_(p5) = COPY $vgpr0
81 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
85 %0:_(p5) = COPY $vgpr0
[all …]
H A Dlegalize-zextload-private.mir14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
17 %0:_(p5) = COPY $vgpr0
30 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
33 %0:_(p5) = COPY $vgpr0
46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
49 %0:_(p5) = COPY $vgpr0
63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
67 %0:_(p5) = COPY $vgpr0
80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
84 %0:_(p5) = COPY $vgpr0
[all …]
H A Dirtranslator-sibling-call.ll27 ; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0.alloca
29 ; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C1]](s32)
69 ; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0.alloca
96 ; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0.alloca
169 ; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
170 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY [[FRAME_INDEX]](p5)
187 ; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
188 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(p5) = COPY [[FRAME_INDEX]](p5)
249 ; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
254 ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[C]](s32)
[all …]
H A Dregbankselect-amdgpu-wave-address.mir12 ; CHECK: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
13 ; CHECK-NEXT: S_ENDPGM 0, implicit [[AMDGPU_WAVE_ADDRESS]](p5)
14 %0:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
26 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
28 ; CHECK-NEXT: G_STORE [[AMDGPU_WAVE_ADDRESS]](p5), [[COPY]](p1) :: (store (p5), addrspace 1)
30 %1:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
31 G_STORE %1, %0 :: (store (p5), addrspace 1)
H A Dbug-legalization-artifact-combiner-dead-def.mir30 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
39 ; GFX10-NEXT: G_STORE [[COPY4]](s32), [[COPY]](p5) :: (store (s32), align 8, addrspace 5)
41 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
43 %0:_(p5) = COPY $vgpr0
54 G_STORE %10(<2 x s32>), %0(p5) :: (store (<2 x s32>), addrspace 5)
66 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
77 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
79 %0:_(p5) = COPY $vgpr0
90 G_STORE %6(s32), %0(p5) :: (store (s32), align 8, addrspace 5)
92 %13:_(p5) = G_PTR_ADD %0, %12(s32)
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SME/
H A Dmova.s24 mova z21.b, p5/m, za0h.b[w14, 10]
54 mova z24.b, p5/m, za0h.b[w14, 3]
78 mova z2.b, p5/m, za0h.b[w15, 9]
98 mov z21.b, p5/m, za0h.b[w14, 10]
128 mov z24.b, p5/m, za0h.b[w14, 3]
152 mov z2.b, p5/m, za0h.b[w15, 9]
203 mova z24.b, p5/m, za0v.b[w14, 3]
227 mova z2.b, p5/m, za0v.b[w15, 9]
301 mov z2.b, p5/m, za0v.b[w15, 9]
376 mova z2.h, p5/m, za1h.h[w15, 1]
[all …]
H A Dpsel.s24 psel p5, p5, p10.b[w13, 6]
51 psel p5, p5, p10.h[w13, 3]
78 psel p5, p5, p10.s[w13, 1]
105 psel p5, p5, p10.d[w13, 0]
H A Dst1b.s24 st1b {za0h.b[w14, 5]}, p5, [x10, x21]
54 st1b {za0h.b[w14, 8]}, p5, [x19, x20]
78 st1b {za0h.b[w15, 2]}, p5, [x9, x1]
96 st1b za0h.b[w14, 5], p5, [x10, x21]
126 st1b za0h.b[w14, 8], p5, [x19, x20]
150 st1b za0h.b[w15, 2], p5, [x9, x1]
171 st1b {za0v.b[w14, 5]}, p5, [x10, x21]
225 st1b {za0v.b[w15, 2]}, p5, [x9, x1]
243 st1b za0v.b[w14, 5], p5, [x10, x21]
273 st1b za0v.b[w14, 8], p5, [x19, x20]
[all …]
H A Dld1b.s24 ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]
54 ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]
78 ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]
96 ld1b za0h.b[w14, 5], p5/z, [x10, x21]
126 ld1b za0h.b[w14, 8], p5/z, [x19, x20]
150 ld1b za0h.b[w15, 2], p5/z, [x9, x1]
171 ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]
225 ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]
243 ld1b za0v.b[w14, 5], p5/z, [x10, x21]
273 ld1b za0v.b[w14, 8], p5/z, [x19, x20]
[all …]
H A Dst1d.s24 st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
54 st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]
78 st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]
96 st1d za2h.d[w14, 1], p5, [x10, x21, lsl #3]
126 st1d za4h.d[w14, 0], p5, [x19, x20, lsl #3]
150 st1d za1h.d[w15, 0], p5, [x9, x1, lsl #3]
171 st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]
225 st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]
243 st1d za2v.d[w14, 1], p5, [x10, x21, lsl #3]
273 st1d za4v.d[w14, 0], p5, [x19, x20, lsl #3]
[all …]
H A Dst1q.s24 st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]
54 st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]
78 st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]
96 st1q za5h.q[w14, 0], p5, [x10, x21, lsl #4]
126 st1q za8h.q[w14, 0], p5, [x19, x20, lsl #4]
150 st1q za2h.q[w15, 0], p5, [x9, x1, lsl #4]
171 st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]
225 st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]
243 st1q za5v.q[w14, 0], p5, [x10, x21, lsl #4]
273 st1q za8v.q[w14, 0], p5, [x19, x20, lsl #4]
[all …]
H A Dst1h.s24 st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]
54 st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]
78 st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]
96 st1h za0h.h[w14, 5], p5, [x10, x21, lsl #1]
126 st1h za1h.h[w14, 0], p5, [x19, x20, lsl #1]
150 st1h za0h.h[w15, 2], p5, [x9, x1, lsl #1]
171 st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]
225 st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]
243 st1h za0v.h[w14, 5], p5, [x10, x21, lsl #1]
273 st1h za1v.h[w14, 0], p5, [x19, x20, lsl #1]
[all …]
H A Dst1w.s24 st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]
54 st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]
78 st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]
96 st1w za1h.s[w14, 1], p5, [x10, x21, lsl #2]
126 st1w za2h.s[w14, 0], p5, [x19, x20, lsl #2]
150 st1w za0h.s[w15, 2], p5, [x9, x1, lsl #2]
171 st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]
225 st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]
243 st1w za1v.s[w14, 1], p5, [x10, x21, lsl #2]
273 st1w za2v.s[w14, 0], p5, [x19, x20, lsl #2]
[all …]
H A Dld1d.s24 ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
54 ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
78 ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
96 ld1d za2h.d[w14, 1], p5/z, [x10, x21, lsl #3]
126 ld1d za4h.d[w14, 0], p5/z, [x19, x20, lsl #3]
150 ld1d za1h.d[w15, 0], p5/z, [x9, x1, lsl #3]
171 ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
225 ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
243 ld1d za2v.d[w14, 1], p5/z, [x10, x21, lsl #3]
273 ld1d za4v.d[w14, 0], p5/z, [x19, x20, lsl #3]
[all …]
H A Dld1h.s24 ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
54 ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
78 ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
96 ld1h za0h.h[w14, 5], p5/z, [x10, x21, lsl #1]
126 ld1h za1h.h[w14, 0], p5/z, [x19, x20, lsl #1]
150 ld1h za0h.h[w15, 2], p5/z, [x9, x1, lsl #1]
171 ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
225 ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
243 ld1h za0v.h[w14, 5], p5/z, [x10, x21, lsl #1]
273 ld1h za1v.h[w14, 0], p5/z, [x19, x20, lsl #1]
[all …]
H A Dld1w.s24 ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
54 ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
78 ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
96 ld1w za1h.s[w14, 1], p5/z, [x10, x21, lsl #2]
126 ld1w za2h.s[w14, 0], p5/z, [x19, x20, lsl #2]
150 ld1w za0h.s[w15, 2], p5/z, [x9, x1, lsl #2]
171 ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
225 ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
243 ld1w za1v.s[w14, 1], p5/z, [x10, x21, lsl #2]
273 ld1w za2v.s[w14, 0], p5/z, [x19, x20, lsl #2]
[all …]
H A Dld1q.s24 ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
54 ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
78 ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
96 ld1q za5h.q[w14, 0], p5/z, [x10, x21, lsl #4]
126 ld1q za8h.q[w14, 0], p5/z, [x19, x20, lsl #4]
150 ld1q za2h.q[w15, 0], p5/z, [x9, x1, lsl #4]
171 ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
225 ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
243 ld1q za5v.q[w14, 0], p5/z, [x10, x21, lsl #4]
273 ld1q za8v.q[w14, 0], p5/z, [x19, x20, lsl #4]
[all …]
/llvm-project-15.0.7/llvm/utils/unittest/googlemock/include/gmock/
H A Dgmock-generated-matchers.h663 p5##_type const p5;\
694 p5##_type const p5;\
701 p3##_type p3, p4##_type p4, p5##_type p5) {\
745 p5##_type const p5;\
778 p5##_type const p5;\
833 p5##_type const p5;\
869 p5##_type const p5;\
928 p5##_type const p5;\
965 p5##_type const p5;\
1028 p5##_type const p5;\
[all …]
H A Dgmock-generated-actions.h545 p5##_type p5;
618 p5##_type p5
1145 p5##_type p5;\
1157 p5##_type p5;\
1232 p5##_type p5;\
1246 p5##_type p5;\
1328 p5##_type p5;\
1343 p5##_type p5;\
1430 p5##_type p5;\
1446 p5##_type p5;\
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dstrcall-no-nul.ll72 %c05 = call i32 @strcmp(i8* %p0, i8* %p5)
76 %c50 = call i32 @strcmp(i8* %p5, i8* %p0)
115 %r = call i8* @strrchr(i8* %p5, i32 0)
132 %s05 = call i8* @strstr(i8* %p0, i8* %p5)
136 %s50 = call i8* @strstr(i8* %p5, i8* %p0)
151 %r = call i64 @strlen(i8* %p5)
163 %r = call i8* @strcpy(i8* %dst, i8* %p5)
175 %r = call i8* @strcpy(i8* %dst, i8* %p5)
287 %i = call i32 @atoi(i8* %p5)
339 %p5 = getelementptr i64, i64* %ps, i32 5
[all …]
/llvm-project-15.0.7/llvm/test/DebugInfo/ARM/
H A Dfloat-stack-arg.ll3 ; Verify that a stack-referencing DBG_VALUE is emitted for p5 at the start of
10 ; float fn1(int p1, int p2, int p3, int p4, float p5) {
11 ; return p5;
18 ; CHECK: ![[P5:[0-9]*]] = !DILocalVariable(name: "p5"
20 define arm_aapcscc float @fn1(i32 %p1, i32 %p2, i32 %p3, i32 %p4, float returned %p5) #0 !dbg !7 {
24 call void @llvm.dbg.value(metadata float %p5, metadata !17, metadata !DIExpression()), !dbg !18
25 ret float %p5, !dbg !19
51 !17 = !DILocalVariable(name: "p5", arg: 5, scope: !7, file: !1, line: 1, type: !10)
/llvm-project-15.0.7/clang/test/Sema/
H A Daix-attr-align.c33 void foo(int p1, int p2, int p3, int p4, int p5, int p6, int p7, int p8, in foo() argument
36 …baz(p1, p2, s.b, p3, b, p5, s); // expected-note {{passing byval argument 's' with potentia… in foo()
37 jaz(p1, p2, a, p3, s.a, p5, t); // no-note in foo()
38 jaz(p1, p2, s.b, p3, b, p5, t); // no-note in foo()
39 vararg_baz(p1, p2, s.b, p3, b, p5, s); // no-note in foo()
40 static_baz(p1, p2, s.b, p3, b, p5, s); // no-note in foo()

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