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/llvm-project-15.0.7/llvm/test/MC/Disassembler/Hexagon/
H A Dalu32_pred.txt8 # CHECK: p3 = r5
13 # CHECK: p3 = r5
18 # CHECK: p3 = r5
23 # CHECK: p3 = r5
30 # CHECK: p3 = r5
35 # CHECK: p3 = r5
40 # CHECK: p3 = r5
45 # CHECK: p3 = r5
54 # CHECK: p3 = r5
57 # CHECK: p3 = r5
[all …]
H A Dxtype_pred.txt12 # CHECK: p3 = cmpb.gt(r17,r21)
14 # CHECK: p3 = cmpb.eq(r17,r21)
16 # CHECK: p3 = cmpb.gtu(r17,r21)
18 # CHECK: p3 = cmpb.eq(r17,#21)
20 # CHECK: p3 = cmpb.gt(r17,#21)
26 # CHECK: p3 = cmph.eq(r17,r21)
28 # CHECK: p3 = cmph.gt(r17,r21)
32 # CHECK: p3 = cmph.eq(r17,#21)
62 # CHECK: r17:16 = mask(p3)
70 # CHECK: p3 = r5
[all …]
H A Dst.txt32 # CHECK: p3 = r5
35 # CHECK: p3 = r5
42 # CHECK: p3 = r5
45 # CHECK: p3 = r5
52 # CHECK: p3 = r5
55 # CHECK: p3 = r5
62 # CHECK: p3 = r5
65 # CHECK: p3 = r5
98 # CHECK: p3 = r5
101 # CHECK: p3 = r5
[all …]
H A Dcr.txt32 # CHECK: p3 = sp1loop0
34 # CHECK: p3 = sp2loop0
36 # CHECK: p3 = sp3loop0
48 # CHECK: p1 = and(p2,and(p3,p3))
52 # CHECK: p1 = and(p2,or(p3,p3))
56 # CHECK: p1 = or(p2,and(p3,p3))
60 # CHECK: p1 = or(p2,or(p3,p3))
62 # CHECK: p1 = and(p2,and(p3,!p3))
64 # CHECK: p1 = and(p2,or(p3,!p3))
68 # CHECK: p1 = or(p2,and(p3,!p3))
[all …]
H A Dld.txt32 # CHECK: p3 = r5
35 # CHECK: p3 = r5
40 # CHECK: p3 = r5
45 # CHECK: p3 = r5
52 # CHECK: p3 = r5
55 # CHECK: p3 = r5
86 # CHECK: p3 = r5
89 # CHECK: p3 = r5
94 # CHECK: p3 = r5
99 # CHECK: p3 = r5
[all …]
H A Dnv_st.txt38 # CHECK: p3 = r5
42 # CHECK: p3 = r5
52 # CHECK: p3 = r5
56 # CHECK: p3 = r5
66 # CHECK: p3 = r5
70 # CHECK: p3 = r5
108 # CHECK: p3 = r5
112 # CHECK: p3 = r5
122 # CHECK: p3 = r5
126 # CHECK: p3 = r5
[all …]
H A Djr.txt10 # CHECK: if (!p3) callr r21
22 # CHECK: p3 = r5
23 # CHECK-NEXT: if (p3.new) jumpr:nt r21
25 # CHECK: p3 = r5
26 # CHECK-NEXT: if (p3.new) jumpr:t r21
28 # CHECK: if (!p3) jumpr:nt r21
30 # CHECK: p3 = r5
31 # CHECK-NEXT: if (!p3.new) jumpr:nt r21
33 # CHECK: p3 = r5
34 # CHECK-NEXT: if (!p3.new) jumpr:t r21
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-load-local.mir5805 ; SI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5811 ; CI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5817 ; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5823 ; VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5829 ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5835 ; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5841 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5847 ; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5853 ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
5859 ; GFX11-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
[all …]
H A Dinst-select-store-atomic-local.mir40 %1:vgpr(p3) = COPY $vgpr1
77 %1:vgpr(p3) = COPY $vgpr1
99 ; GFX6-NEXT: G_STORE [[COPY]](p3), [[COPY1]](p3) :: (store seq_cst (p3), addrspace 3)
106 ; GFX7-NEXT: G_STORE [[COPY]](p3), [[COPY1]](p3) :: (store seq_cst (p3), addrspace 3)
112 ; GFX9-NEXT: G_STORE [[COPY]](p3), [[COPY1]](p3) :: (store seq_cst (p3), addrspace 3)
113 %0:vgpr(p3) = COPY $vgpr0
114 %1:vgpr(p3) = COPY $vgpr1
151 %1:vgpr(p3) = COPY $vgpr1
188 %1:vgpr(p3) = COPY $vgpr1
225 %1:vgpr(p3) = COPY $vgpr2
[all …]
H A Dinst-select-load-atomic-local.mir39 %0:vgpr(p3) = COPY $vgpr0
76 %0:vgpr(p3) = COPY $vgpr0
98 …; GFX6-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p3) :: (load seq_cst (p3), addrspace 3)
105 …; GFX7-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p3) :: (load seq_cst (p3), addrspace 3)
111 …; GFX9-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p3) :: (load seq_cst (p3), addrspace 3)
113 %0:vgpr(p3) = COPY $vgpr0
114 %1:vgpr(p3) = G_LOAD %0 :: (load seq_cst (p3), align 4, addrspace 3)
150 %0:vgpr(p3) = COPY $vgpr0
187 %0:vgpr(p3) = COPY $vgpr0
224 %0:vgpr(p3) = COPY $vgpr0
[all …]
H A Dlegalize-zextload-local.mir13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
16 %0:_(p3) = COPY $vgpr0
29 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
32 %0:_(p3) = COPY $vgpr0
45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
48 %0:_(p3) = COPY $vgpr0
62 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
66 %0:_(p3) = COPY $vgpr0
79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
83 %0:_(p3) = COPY $vgpr0
[all …]
H A Dlegalize-sextload-local.mir13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
16 %0:_(p3) = COPY $vgpr0
29 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
32 %0:_(p3) = COPY $vgpr0
45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
48 %0:_(p3) = COPY $vgpr0
62 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
66 %0:_(p3) = COPY $vgpr0
79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
83 %0:_(p3) = COPY $vgpr0
[all …]
H A Dregbankselect-amdgcn.update.dpp.mir15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
17 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
19 …]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), [[COPY2]](p3), [[COPY3]](s32), 0,…
20 %0:_(p3) = COPY $sgpr0
37 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
39 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
41 %0:_(p3) = COPY $sgpr0
58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
62 %0:_(p3) = COPY $vgpr0
79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
[all …]
H A Dlegalize-ptr-add.mir77 %0:_(p3) = COPY $vgpr0
79 %2:_(p3) = G_PTR_ADD %0, %1
197 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
201 …; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[PTR_ADD]](p3), [[PTR_ADD1]](…
285 %0:_(p3) = COPY $vgpr0
288 %3:_(p3) = G_PTR_ADD %0, %2
306 %0:_(p3) = COPY $vgpr0
375 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
383 …; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[PTR_ADD]](p3), [[PTR_ADD1]](…
402 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
[all …]
H A Dcombine-add-nullptr.mir21 %3:_(p3) = G_CONSTANT i32 0
22 %4:_(p3) = G_PTR_ADD %3, %2(s32)
23 %5:_(s32) = G_PTRTOINT %4(p3)
44 %2:_(p3) = G_CONSTANT i32 0
46 %4:_(p3) = G_PTR_ADD %2:_, %3:_(s32)
47 %5:_(s32) = G_PTRTOINT %4:_(p3)
73 %5:_(p3) = G_CONSTANT i32 0
74 %6:_(<2 x p3>) = G_BUILD_VECTOR %5:_(p3), %5:_(p3)
75 %7:_(<2 x p3>) = G_PTR_ADD %6, %4(<2 x s32>)
76 %8:_(<2 x s32>) = G_PTRTOINT %7(<2 x p3>)
H A Dregbankselect-amdgcn.ds.append.mir15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
16 …%[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.append), [[COPY]](p3), 0
17 %0:_(p3) = COPY $sgpr0
32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(p3) = COPY $vgpr0
33 …; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(p3) = V_READFIRSTLANE_B32 [[COPY]](p3), imp…
34 …32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.append), [[V_READFIRSTLANE_B32_]](p3), 0
35 %0:_(p3) = COPY $vgpr0
H A Dregbankselect-amdgcn.ds.consume.mir15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
16 …[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.consume), [[COPY]](p3), 0
17 %0:_(p3) = COPY $sgpr0
32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(p3) = COPY $vgpr0
33 …; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(p3) = V_READFIRSTLANE_B32 [[COPY]](p3), imp…
34 …2) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.consume), [[V_READFIRSTLANE_B32_]](p3), 0
35 %0:_(p3) = COPY $vgpr0
H A Dlegalize-addrspacecast.mir342 %0:_(p3) = COPY $vgpr0
365 ; VI-NEXT: $vgpr0 = COPY [[SELECT]](p3)
387 %1:_(p3) = G_ADDRSPACE_CAST %0
495 ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
510 … ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
525 ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
528 %1:_(<2 x p3>) = G_ADDRSPACE_CAST %0
546 ; VI-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
570 ; GFX9-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
592 ; SI-NEXT: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
[all …]
/llvm-project-15.0.7/llvm/utils/unittest/googlemock/include/gmock/
H A Dgmock-generated-matchers.h512 p3##_type const p3;\
539 p3##_type const p3;\
546 p3##_type p3) {\
585 p3##_type const p3;\
614 p3##_type const p3;\
661 p3##_type const p3;\
692 p3##_type const p3;\
776 p3##_type const p3;\
867 p3##_type const p3;\
963 p3##_type const p3;\
[all …]
H A Dgmock-generated-actions.h985 p3##_type p3;\
995 p3##_type p3;\
1062 p3##_type p3;\
1073 p3##_type p3;\
1143 p3##_type p3;\
1155 p3##_type p3;\
1230 p3##_type p3;\
1244 p3##_type p3;\
1341 p3##_type p3;\
1444 p3##_type p3;\
[all …]
/llvm-project-15.0.7/libc/AOR_v20.02/string/aarch64/
H A Dstrrchr-sve.S38 cmpeq p3.b, p1/z, z0.b, 0 /* search for 0 */
41 cmpeq p3.b, p1/z, z0.b, z1.b /* search for c; no eos */
45 mov p2.b, p3.b /* save current search */
50 1: cmpeq p3.b, p0/z, z0.b, 0 /* search for 0 */
60 mov p2.b, p3.b /* save current search */
65 3: brka p3.b, p1/z, p3.b /* mask after first 0 */
66 cmpeq p3.b, p3/z, z0.b, z1.b /* search for c not after eos */
72 mov p3.b, p2.b /* restore saved search */
76 4: rev p3.b, p3.b /* reverse the bits */
77 brka p3.b, p1/z, p3.b /* find position of last match */
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dstores_vectorize.ll5 ; long a = p3[0] = 5;
8 ; p3[0] >>= 5;
9 ; p3[1] >>= 5;
10 ; p3[2] >>= 5;
11 ; p3[3] >>= 5;
13 ; p4[0] += p1[p3[0] & a];
44 store i64 5, i64* %p3, align 8
53 %2 = load i64, i64* %p3, align 8
55 store i64 %shr, i64* %p3, align 8
160 store i64 5, i64* %p3, align 8
[all …]
/llvm-project-15.0.7/flang/test/Semantics/
H A Dallocate04.f9032 class(B), pointer :: p3, p4(:) local
48 allocate(p3%y)
60 allocate(B:: p3%y, p4(2)%y)
66 allocate(p1, p2(2), MOLD = p3)
67 allocate(p3%y, p4(2)%y, MOLD = B(5))
73 allocate(p1, p2(2), SOURCE = p3)
74 allocate(p3%y, p4(2)%y, SOURCE = B(5))
78 allocate(p3, p4(2))
/llvm-project-15.0.7/llvm/test/MC/AArch64/SME/
H A Dmova.s30 mova z23.b, p3/m, za0h.b[w15, 13]
42 mova z5.b, p3/m, za0h.b[w12, 1]
104 mov z23.b, p3/m, za0h.b[w15, 13]
116 mov z5.b, p3/m, za0h.b[w12, 1]
179 mova z23.b, p3/m, za0v.b[w15, 13]
191 mova z5.b, p3/m, za0v.b[w12, 1]
265 mov z5.b, p3/m, za0v.b[w12, 1]
340 mova z5.h, p3/m, za0h.h[w12, 1]
414 mov z5.h, p3/m, za0h.h[w12, 1]
489 mova z5.h, p3/m, za0v.h[w12, 1]
[all …]
/llvm-project-15.0.7/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.weak/util.smartptr.ownerless/
H A Downer_less.pass.cpp61 const std::shared_ptr<int> p3(new int); in main() local
64 const std::weak_ptr<int> w3(p3); in main()
78 assert(cs(p1 ,p3) || cs(p3, p1)); in main()
79 assert(cs(p3, p1) == cs(p3, p2)); in main()
84 assert(cs(p1, w3) || cs(p3, w1)); in main()
85 assert(cs(p3, w1) == cs(p3, w2)); in main()
107 assert(cs(w1, p3) || cs(w3, p1)); in main()

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