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/llvm-project-15.0.7/clang/test/CodeGen/
H A Dmult-alt-generic.c27 register int out0 = 0; in single_o() local
42 register int out0 = 0; in single_lt() local
53 register int out0 = 0; in single_gt() local
64 register int out0 = 0; in single_r() local
73 register int out0 = 0; in single_i() local
81 register int out0 = 0; in single_n() local
105 register int out0 = 0; in single_s() local
112 register int out0 = 0; in single_g() local
125 register int out0 = 0; in single_X() local
144 register int out0 = 0; in single_p() local
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmult-alt-generic-i686.ll18 %out0 = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
32 %out0 = alloca i32, align 4
47 %out0 = alloca i32, align 4
62 %out0 = alloca i32, align 4
74 %out0 = alloca i32, align 4
83 %out0 = alloca i32, align 4
112 %out0 = alloca i32, align 4
119 %out0 = alloca i32, align 4
136 %out0 = alloca i32, align 4
[all …]
H A Dmult-alt-generic-x86_64.ll18 %out0 = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
32 %out0 = alloca i32, align 4
47 %out0 = alloca i32, align 4
62 %out0 = alloca i32, align 4
74 %out0 = alloca i32, align 4
83 %out0 = alloca i32, align 4
112 %out0 = alloca i32, align 4
119 %out0 = alloca i32, align 4
136 %out0 = alloca i32, align 4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dmult-alt-generic-powerpc64.ll18 %out0 = alloca i32, align 4
32 %out0 = alloca i32, align 4
47 %out0 = alloca i32, align 4
62 %out0 = alloca i32, align 4
74 %out0 = alloca i32, align 4
83 %out0 = alloca i32, align 4
112 %out0 = alloca i32, align 4
119 %out0 = alloca i32, align 4
136 %out0 = alloca i32, align 4
159 %out0 = alloca i32, align 4
[all …]
H A Dmult-alt-generic-powerpc.ll18 %out0 = alloca i32, align 4
32 %out0 = alloca i32, align 4
47 %out0 = alloca i32, align 4
62 %out0 = alloca i32, align 4
74 %out0 = alloca i32, align 4
83 %out0 = alloca i32, align 4
112 %out0 = alloca i32, align 4
119 %out0 = alloca i32, align 4
136 %out0 = alloca i32, align 4
159 %out0 = alloca i32, align 4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dmult-alt-generic-arm.ll18 %out0 = alloca i32, align 4
32 %out0 = alloca i32, align 4
47 %out0 = alloca i32, align 4
62 %out0 = alloca i32, align 4
74 %out0 = alloca i32, align 4
83 %out0 = alloca i32, align 4
112 %out0 = alloca i32, align 4
119 %out0 = alloca i32, align 4
136 %out0 = alloca i32, align 4
160 %out0 = alloca i32, align 4
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/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dmult-alt-generic-sparc.ll18 %out0 = alloca i32, align 4
32 %out0 = alloca i32, align 4
47 %out0 = alloca i32, align 4
62 %out0 = alloca i32, align 4
74 %out0 = alloca i32, align 4
83 %out0 = alloca i32, align 4
112 %out0 = alloca i32, align 4
119 %out0 = alloca i32, align 4
136 %out0 = alloca i32, align 4
160 %out0 = alloca i32, align 4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/MSP430/
H A Dmult-alt-generic-msp430.ll18 %out0 = alloca i16, align 2
20 store i16 0, i16* %out0, align 2
32 %out0 = alloca i16, align 2
47 %out0 = alloca i16, align 2
62 %out0 = alloca i16, align 2
74 %out0 = alloca i16, align 2
83 %out0 = alloca i16, align 2
112 %out0 = alloca i16, align 2
119 %out0 = alloca i16, align 2
136 %out0 = alloca i16, align 2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddefault-fp-mode.ll7 store float 0.0, float addrspace(1)* %out0
16 store float 0.0, float addrspace(1)* %out0
25 store float 0.0, float addrspace(1)* %out0
34 store float 0.0, float addrspace(1)* %out0
43 store float 0.0, float addrspace(1)* %out0
52 store float 0.0, float addrspace(1)* %out0
61 store half 0.0, half addrspace(1)* %out0
70 store half 0.0, half addrspace(1)* %out0
79 store half 0.0, half addrspace(1)* %out0
89 store float 0.0, float addrspace(1)* %out0
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H A Dhsa-fp-mode.ll7 define amdgpu_kernel void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #…
8 store float 0.0, float addrspace(1)* %out0
17 define amdgpu_kernel void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #…
18 store float 0.0, float addrspace(1)* %out0
28 store float 0.0, float addrspace(1)* %out0
38 store float 0.0, float addrspace(1)* %out0
48 store float 0.0, float addrspace(1)* %out0
58 store float 0.0, float addrspace(1)* %out0
68 store float 0.0, float addrspace(1)* %out0
78 store float 0.0, float addrspace(1)* %out0
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H A Dextract-vector-elt-build-vector-combine.ll16 …e amdgpu_kernel void @store_build_vector_multiple_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
30 store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
58 …_kernel void @store_build_vector_multiple_extract_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
82 store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
102 …oid @store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64(<2 x i64> addrspace(1)* noalias %out0,
117 store <2 x i64> %bc.vec3, <2 x i64> addrspace(1)* %out0
H A Dgfx902-without-xnack.ll4 define amdgpu_kernel void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounw…
5 store float 0.0, float addrspace(1)* %out0
H A Dhsa-default-device.ll7 define amdgpu_kernel void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounw…
8 store float 0.0, float addrspace(1)* %out0
H A Dsminmax.v2i16.ll166 define amdgpu_kernel void @s_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %…
171 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
179 define amdgpu_kernel void @v_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %…
187 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
197 define amdgpu_kernel void @s_min_max_v4i16(<4 x i16> addrspace(1)* %out0, <4 x i16> addrspace(1)* %…
202 store volatile <4 x i16> %sel0, <4 x i16> addrspace(1)* %out0, align 4
208 define amdgpu_kernel void @v_min_max_v2i16_user(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(…
216 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
225 define amdgpu_kernel void @u_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %…
230 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
H A Dsminmax.ll204 define amdgpu_kernel void @s_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, [8 x i32…
209 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
220 define amdgpu_kernel void @v_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addr…
228 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
242 define amdgpu_kernel void @s_min_max_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %…
247 store volatile <4 x i32> %sel0, <4 x i32> addrspace(1)* %out0, align 4
257 define amdgpu_kernel void @v_min_max_i32_user(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32…
265 store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
H A Dschedule-global-loads.ll13 define amdgpu_kernel void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out…
17 store i32 %load0, i32 addrspace(1)* %out0, align 4
H A Dglobal_smrd.ll79 …ep_alias_arg(i32 addrspace(1)* noalias %in, [8 x i32], i32 addrspace(1)* %out0, [8 x i32], i32 add…
80 store i32 0, i32 addrspace(1)* %out0
91 define amdgpu_kernel void @memdep(i32 addrspace(1)* %in, [8 x i32], i32 addrspace(1)* %out0, [8 x i…
92 store i32 0, i32 addrspace(1)* %out0
H A Dstore-clobbers-load.ll34 define amdgpu_kernel void @atomicrmw_clobbers_load(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1…
40 store i32 %val, i32 addrspace(1)* %out0, align 4
H A Dfneg-fabs.f16.ll138 define amdgpu_kernel void @s_fneg_multi_use_fabs_v2f16(<2 x half> addrspace(1)* %out0, <2 x half> a…
141 store <2 x half> %fabs, <2 x half> addrspace(1)* %out0
149 define amdgpu_kernel void @s_fneg_multi_use_fabs_foldable_neg_v2f16(<2 x half> addrspace(1)* %out0,…
153 store <2 x half> %fabs, <2 x half> addrspace(1)* %out0
H A Dindirect-addressing-si-pregfx9.ll26 define amdgpu_kernel void @insert_vgpr_offset_multiple_in_block(<16 x i32> addrspace(1)* %out0, <16…
36 store volatile <16 x i32> %vec2, <16 x i32> addrspace(1)* %out0
H A Dschedule-kernel-arg-loads.ll10 define amdgpu_kernel void @cluster_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 …
11 store i32 %x, i32 addrspace(1)* %out0, align 4
H A Damdhsa-trap-num-sgprs.ll8 i32 addrspace(1)* %out0, i32 %in0,
39 store i32 %in0, i32 addrspace(1)* %out0
H A Dindirect-addressing-si-gfx9.ll21 define amdgpu_kernel void @insert_vgpr_offset_multiple_in_block(<16 x i32> addrspace(1)* %out0, <16…
31 store volatile <16 x i32> %vec2, <16 x i32> addrspace(1)* %out0
/llvm-project-15.0.7/mlir/test/Analysis/
H A Dtest-match-reduction.mlir16 ^bb0(%in0: f32, %out0: f32):
17 %add = arith.addf %in0, %out0 : f32
53 ^bb0(%in0: f32, %out0: f32):
54 %cmp = arith.cmpf ogt, %in0, %out0 : f32
55 %sel = arith.select %cmp, %in0, %out0 : f32
73 ^bb0(%in0: f32, %out0: f32):
76 %add = arith.addf %sub, %out0 : f32
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dptrtoint.ll42 store i64 %p0, i64* %out0
79 store i64 %p0, i64* %out0
106 store i64 %p0, i64* %out0
130 store i64 %p0, i64* %out0
154 store i64 %p0, i64* %out0
167 store i64 %p0, i64* %out0
186 store i64 %p0, i64* %out0
210 store i64 %p0, i64* %out0
295 store i64 %p0, i64* %out0
319 store i64 %p0, i64* %out0
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