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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dtail-dup.ll12 define i32 @fn(i32* nocapture %opcodes) nounwind readonly ssp {
14 %0 = load i32, i32* %opcodes, align 4
20 %1 = load i32, i32* %opcodes.addr.0, align 4
26 %2 = load i32, i32* %opcodes.addr.0, align 4
32 …%opcodes.pn = phi i32* [ %opcodes, %entry ], [ %opcodes.addr.0, %DECREMENT ], [ %opcodes.addr.0, %…
34 %opcodes.addr.0 = getelementptr inbounds i32, i32* %opcodes.pn, i32 1
/llvm-project-15.0.7/lldb/include/lldb/Symbol/
H A DUnwindPlan.h156 *opcodes = m_location.expr.opcodes; in GetDWARFExpr()
159 *opcodes = nullptr; in GetDWARFExpr()
164 void SetAtDWARFExpression(const uint8_t *opcodes, uint32_t len);
166 void SetIsDWARFExpression(const uint8_t *opcodes, uint32_t len);
170 return m_location.expr.opcodes; in GetDWARFExpressionBytes()
192 const uint8_t *opcodes; member
246 m_value.expr.opcodes = opcodes; in SetIsDWARFExpression()
281 *opcodes = m_value.expr.opcodes; in GetDWARFExpr()
284 *opcodes = nullptr; in GetDWARFExpr()
291 return m_value.expr.opcodes; in GetDWARFExpressionBytes()
[all …]
/llvm-project-15.0.7/lldb/source/Expression/
H A DDWARFExpression.cpp840 if (opcodes.GetByteSize() == 0) { in Evaluate()
886 while (opcodes.ValidOffset(offset)) { in Evaluate()
888 const uint8_t op = opcodes.GetU8(&offset); in Evaluate()
1054 uint8_t size = opcodes.GetU8(&offset); in Evaluate()
1661 if (new_offset <= opcodes.GetByteSize()) in Evaluate()
1923 reg_num = opcodes.GetULEB128(&offset); in Evaluate()
1986 reg_num = opcodes.GetULEB128(&offset); in Evaluate()
2624 DataExtractor opcodes(m_data); in MatchesOperand() local
2627 uint8_t opcode = opcodes.GetU8(&op_offset); in MatchesOperand()
2660 offset = opcodes.GetSLEB128(&op_offset); in MatchesOperand()
[all …]
/llvm-project-15.0.7/lld/MachO/
H A DSyntheticSections.cpp379 opcodes.push_back( in encodeBinding()
391 opcodes.push_back( in encodeBinding()
409 opcodes[pWrite].data = opcodes[i].data; in optimizeOpcodes()
412 opcodes[pWrite] = opcodes[i - 1]; in optimizeOpcodes()
415 if (i == opcodes.size()) in optimizeOpcodes()
416 opcodes[pWrite] = opcodes[i - 1]; in optimizeOpcodes()
424 (opcodes[i].data == opcodes[i - 1].data)) { in optimizeOpcodes()
427 opcodes[pWrite].data = opcodes[i].data; in optimizeOpcodes()
431 (opcodes[i].data == opcodes[i - 1].data)) { in optimizeOpcodes()
436 opcodes[pWrite] = opcodes[i - 1]; in optimizeOpcodes()
[all …]
/llvm-project-15.0.7/lldb/source/Symbol/
H A DUnwindPlan.cpp45 return !memcmp(m_location.expr.opcodes, rhs.m_location.expr.opcodes, in operator ==()
56 const uint8_t *opcodes, uint32_t len) { in SetAtDWARFExpression() argument
58 m_location.expr.opcodes = opcodes; in SetAtDWARFExpression()
65 const uint8_t *opcodes, uint32_t len) { in SetIsDWARFExpression() argument
67 m_location.expr.opcodes = opcodes; in SetIsDWARFExpression()
150 s, llvm::makeArrayRef(m_location.expr.opcodes, m_location.expr.length), in Dump()
183 return !memcmp(m_value.expr.opcodes, rhs.m_value.expr.opcodes, in operator ==()
205 llvm::makeArrayRef(m_value.expr.opcodes, m_value.expr.length), in Dump()
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/ARM/
H A Dunwind-non-relocatable.test99 Value: 0x80B0B0B0 ## arbitrary opcodes.
102 Value: 0x809B8480 ## arbitrary opcodes.
105 Value: 0x80B0B0B0 ## arbitrary opcodes.
111 Value: 0x80B0B0B0 ## arbitrary opcodes.
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A D2009-12-17-pre-regalloc-taildup.ll13 define i32 @interpret_threaded(i8* nocapture %opcodes) nounwind readonly optsize {
15 %0 = load i8, i8* %opcodes, align 1 ; <i8> [#uses=1]
24 %opcodes_addr.0 = getelementptr i8, i8* %opcodes, i32 %indvar ; <i8*> [#uses=4]
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td84 // set of opcodes.
165 // Check that the instruction opcode is one of the opcodes in set `Opcodes`.
213 // `opcodes` list, and each case is associated with MCStatement `caseStmt`.
214 class MCOpcodeSwitchCase<list<Instruction> opcodes, MCStatement caseStmt> {
215 list<Instruction> Opcodes = opcodes;
282 // a) MI's opcode is in the `opcodes` set, and
294 class InstructionEquivalenceClass<list<Instruction> opcodes,
297 list<Instruction> Opcodes = opcodes;
308 class DepBreakingClass<list<Instruction> opcodes, MCInstPredicate pred,
310 : InstructionEquivalenceClass<opcodes, pred, BrokenDeps>;
/llvm-project-15.0.7/llvm/test/ExecutionEngine/JITLink/X86/
H A DELF_x86-64_got_plt_optimizations.s24 # We need check both the target address and the instruction opcodes
38 # We need check both the target address and the instruction opcodes
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BdVer2/
H A Dstore-throughput.s88 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
94 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
318 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
324 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
548 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
555 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
780 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
785 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
H A Dload-throughput.s88 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
94 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
318 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
324 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
548 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
554 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
780 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
785 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
H A Dload-store-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
89 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
317 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
325 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
553 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
560 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/
H A Doption-all-stats-1.s39 # FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
45 # FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
H A Doption-all-stats-2.s40 # FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
46 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
H A Doption-all-views-1.s61 # FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
67 # FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
H A Doption-all-views-2.s60 # ALL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
66 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-all-stats.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
52 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
H A DA55-all-views.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
52 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
H A DA55-out-of-order-retire.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
51 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
H A DA55-in-order-retire.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
52 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Barcelona/
H A Dload-store-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
87 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
275 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
281 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
469 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
475 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
H A Dstore-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
88 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
277 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
284 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
473 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
480 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
H A Dload-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
87 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
275 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
281 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
469 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
475 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
/llvm-project-15.0.7/clang/lib/AST/Interp/
H A DOpcodes.td9 // Helper file used to generate opcodes, the interpreter and the disassembler.
89 // Record describing all opcodes.
109 // Jump opcodes
387 // Comparison opcodes.
/llvm-project-15.0.7/lld/test/ELF/
H A Davr-reloc.s46 ;; The disassembler is not yet able to decode those opcodes
64 ;; The disassembler is not yet able to decode those opcodes

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