| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | BitsInit.td | 7 bits<2> opc2 = { 1, 0 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
17 // CHECK: bits<2> opc2 = { 1, 0 };
|
| /llvm-project-15.0.7/flang/test/Semantics/ |
| H A D | symbol15.f90 | 52 real, pointer :: opc2 => null() component
102 real, pointer :: opc2 => null() component
|
| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
217 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
225 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
234 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
250 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
255 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
261 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
266 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 5360 timm:$CRm, timm:$opc2)]>,
5366 bits<3> opc2;
5371 let Inst{7-5} = opc2;
5391 bits<3> opc2;
5396 let Inst{7-5} = opc2;
5593 bits<3> opc2;
5600 let Inst{7-5} = opc2;
5620 imm0_7:$opc2), []>,
5640 bits<3> opc2;
5647 let Inst{7-5} = opc2;
[all …]
|
| H A D | ARMInstrThumb2.td | 4535 bits<3> opc2;
4542 let Inst{7-5} = opc2;
4575 c_imm:$CRm, imm0_7:$opc2),
4577 timm:$CRm, timm:$opc2)]>,
4584 c_imm:$CRm, imm0_7:$opc2),
4586 timm:$CRm, timm:$opc2)]> {
4648 timm:$CRm, timm:$opc2)]> {
4655 bits<3> opc2;
4660 let Inst{7-5} = opc2;
4681 bits<3> opc2;
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrMMX.td | 51 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
65 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
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| H A D | X86InstrSSE.td | 3556 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3579 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3588 multiclass PDI_binop_rmi_all<bits<8> opc, bits<8> opc2, Format ImmForm,
3595 defm V#NAME : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3599 defm V#NAME#Y : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3604 defm NAME : PDI_binop_rmi<opc, opc2, ImmForm, OpcodeStr, OpNode, OpNode2,
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| H A D | X86InstrAVX512.td | 3158 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
3166 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode,
3168 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 4472 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
4482 let Inst{11-10} = opc2;
4512 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
4514 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
10886 bit opc1, bit opc2, RegisterOperand dst_reg,
10914 let Inst{12} = opc2;
10924 multiclass SIMDIndexedTiedComplexHSD<bit opc1, bit opc2, Operand rottype,
10927 def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
10935 def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
10945 def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
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| H A D | SVEInstrFormats.td | 2557 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm, bit streaming_sve = 0b0>
2567 let Inst{20-16} = opc2{4-0};
|