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Searched refs:off1 (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/IRCE/
H A Dempty_ranges.ll22 ; CHECK-NEXT: %off1 = add i32 %idx, 30
23 ; CHECK-NEXT: %c2 = icmp slt i32 %off1, 40
51 %off1 = add i32 %idx, 30
52 %c2 = icmp slt i32 %off1, 40
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvldm-liveness.ll14 %off1 = getelementptr float, float* %ptr, i32 1
15 %val1 = load float, float* %off1
/llvm-project-15.0.7/lld/test/ELF/
H A Damdgpu-tid.s4 …mdhsa -mcpu=gfx906 -mattr=-xnack --amdhsa-code-object-version=4 -filetype=obj %s -o %t-xnack-off1.o
5 # RUN: ld.lld -shared %t-xnack-off0.o %t-xnack-off1.o -o %t-xnack-off2.so
26 …a -mcpu=gfx906 -mattr=-sramecc --amdhsa-code-object-version=4 -filetype=obj %s -o %t-sramecc-off1.o
27 # RUN: ld.lld -shared %t-sramecc-off0.o %t-sramecc-off1.o -o %t-sramecc-off2.so
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dunaligned-01.ll12 %off1 = getelementptr i8, i8 *%ptr, i64 1
16 store i8 1, i8 *%off1
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dfold-addi-loadstore.ll8 ; (load (addi base, off1), off2) -> (load base, off1+off2)
9 ; (store val, (addi base, off1), off2) -> (store val, base, off1+off2)
10 ; This is possible when the off1+off2 continues to fit the 12-bit immediate.
11 ; Check if we do the fold under various conditions. If off1 is (the low part of)
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Dsink-addrmode.ll70 define void @test_phi_twogep_nonconst_offset(i32* %ptr, i32 %value, i32 %off1, i32 %off2) {
73 ; CHECK: phi i32 [ %off2, %if.else ], [ %off1, %if.then ]
79 %gep1 = getelementptr inbounds i32, i32* %ptr, i32 %off1
179 define void @test_select_twogep_nonconst_offset(i32* %ptr, i32 %value, i32 %off1, i32 %off2) {
182 ; CHECK: select i1 %cmp, i32 %off1, i32 %off2
185 %gep1 = getelementptr inbounds i32, i32* %ptr, i32 %off1
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dno-unique-address.cpp36 Empty1 HasEmptyDuplicates::*off1 = &HasEmptyDuplicates::e1; variable
/llvm-project-15.0.7/mlir/test/Conversion/MemRefToLLVM/
H A Dconvert-dynamic-memref-ops.mlir176 // CHECK-NEXT: %[[off1:.*]] = llvm.add %[[offI]], %[[J]] : i64
177 // CHECK-NEXT: %[[addr:.*]] = llvm.getelementptr %[[ptr]][%[[off1]]] : (!llvm.ptr<f32>, i64) -> !…
193 // CHECK-NEXT: %[[off1:.*]] = llvm.add %[[offI]], %[[J]] : i64
194 // CHECK-NEXT: %[[addr:.*]] = llvm.getelementptr %[[ptr]][%[[off1]]] : (!llvm.ptr<f32>, i64) -> !…
210 // CHECK-NEXT: %[[off1:.*]] = llvm.add %[[offI]], %[[J]] : i64
211 // CHECK-NEXT: %[[addr:.*]] = llvm.getelementptr %[[ptr]][%[[off1]]] : (!llvm.ptr<f32>, i64) -> !l…
240 // CHECK-NEXT: %[[off1:.*]] = llvm.add %[[offI]], %[[J]] : i64
241 // CHECK-NEXT: %[[addr:.*]] = llvm.getelementptr %[[ptr]][%[[off1]]] : (!llvm.ptr<f32>, i64) -> !…
257 // CHECK-NEXT: %[[off1:.*]] = llvm.add %[[offI]], %[[J]] : i64
258 // CHECK-NEXT: %[[addr:.*]] = llvm.getelementptr %[[ptr]][%[[off1]]] : (!llvm.ptr<f32>, i64) -> !…
H A Dconvert-static-memref-ops.mlir136 // CHECK: %[[off1:.*]] = llvm.add %[[offI]], %[[JJ]] : i64
137 // CHECK: %[[addr:.*]] = llvm.getelementptr %[[ptr]][%[[off1]]] : (!llvm.ptr<f32>, i64) -> !llvm.p…
164 // CHECK: %[[off1:.*]] = llvm.add %[[offI]], %[[JJ]] : i64
165 // CHECK: %[[addr:.*]] = llvm.getelementptr %[[ptr]][%[[off1]]] : (!llvm.ptr<f32>, i64) -> !llvm.pt…
/llvm-project-15.0.7/llvm/test/Transforms/CorrelatedValuePropagation/
H A Dicmp.ll561 %idx.off1 = add i64 %idx, -5
562 %cmp1 = icmp ult i64 %idx.off1, 3
582 %idx.off1 = add i64 %idx, -5
583 %cmp1 = icmp ult i64 %idx.off1, 3
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dloadorder.ll416 define i32 @reduce_blockstrided4x4(i8* nocapture noundef readonly %p1, i32 noundef %off1, i8* nocap…
460 %idx.ext = sext i32 %off1 to i64
937 define void @store_blockstrided4x4(i8* nocapture noundef readonly %p1, i32 noundef %off1, i8* nocap…
990 %idx.ext = sext i32 %off1 to i64