Home
last modified time | relevance | path

Searched refs:of (Results 1 – 25 of 6086) sorted by relevance

12345678910>>...244

/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dwineh-coreclr.ll172 ; ^ offset of end of clause
176 ; ^ offset of end of handler
185 ; ^ offset of end of clause
189 ; ^ offset of end of handler
198 ; ^ offset of end of clause
202 ; ^ offset of end of handler
214 ; ^ offset of end of clause
218 ; ^ offset of end of handler
227 ; ^ offset of end of clause
243 ; ^ offset of end of clause
[all …]
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DDiagnosticASTKinds.td145 "%select{read of|read of|assignment to|increment of|decrement of|"
150 "%select{read of|read of|assignment to|increment of|decrement of|"
162 "%select{read of|read of|assignment to|increment of|decrement of|"
166 "%select{read of|read of|assignment to|increment of|decrement of|"
173 "%select{read of|read of|assignment to|increment of|decrement of|"
187 "%select{read of|read of|assignment to|increment of|decrement of|"
192 "%select{read of|read of|assignment to|increment of|decrement of|"
198 "%select{read of|read of|assignment to|increment of|decrement of|"
204 "%select{read of|read of|assignment to|increment of|decrement of|"
213 "%select{read of|read of|assignment to|increment of|decrement of|"
[all …]
/llvm-project-15.0.7/llvm/include/llvm/BinaryFormat/
H A DDynamicTags.def44 DYNAMIC_TAG(NULL, 0) // Marks end of dynamic array.
48 DYNAMIC_TAG(HASH, 4) // Address of symbolic hash table.
52 DYNAMIC_TAG(RELASZ, 8) // Size of Rela relocation table.
54 DYNAMIC_TAG(STRSZ, 10) // Total size of the string table.
55 DYNAMIC_TAG(SYMENT, 11) // Size of a symbol table entry.
62 DYNAMIC_TAG(RELSZ, 18) // Size of Rel relocation table.
71 DYNAMIC_TAG(INIT_ARRAYSZ, 27) // Size of DT_INIT_ARRAY.
72 DYNAMIC_TAG(FINI_ARRAYSZ, 28) // Size of DT_FINI_ARRAY.
85 DYNAMIC_TAG(RELRSZ, 35) // Size of Relr relocation table.
87 DYNAMIC_TAG(RELRENT, 37) // Size of a Relr relocation entry.
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Darith.ll35 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
54 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
73 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
92 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
168 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
187 ; GLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
1184 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
1188 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
1192 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
1200 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
H A Dtrunc.ll25 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
33 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
41 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
97 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
173 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
240 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
307 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
374 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
441 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
1082 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dvector-extract.ll29 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
43 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
57 ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
94 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
113 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
170 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
184 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
212 ; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
226 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
254 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dicmp.ll40 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
63 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
86 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
109 ; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
132 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
155 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
178 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
293 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
344 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
367 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dfcmp.ll28 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
41 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
54 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
67 ; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
80 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
93 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
135 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
148 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
200 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
307 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dmul32.ll40 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
58 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
76 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
94 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
112 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
148 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
166 ; GLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
203 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
257 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
311 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
H A Dload_store.ll61 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
112 ; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
163 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
214 ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
472 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
658 ; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
844 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
1307 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
1409 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
2090 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dextend.ll26 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
35 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
44 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
107 ; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
135 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
152 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
169 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
186 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
203 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
369 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dmin-legal-vector-width.ll15 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
39 ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
47 ; SKX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
64 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
88 ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
96 ; SKX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
114 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
141 ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
150 ; SKX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
169 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
H A Dfptosi.ll19 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
26 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
33 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
54 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
69 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
83 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
90 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
104 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
133 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
147 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Duitofp.ll19 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
26 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
33 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
40 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
62 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
69 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
76 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
83 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
105 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
119 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dsitofp.ll19 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
26 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
33 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
40 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
62 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
69 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
76 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
83 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
105 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
119 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
[all …]
H A Dcast.ll20 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
42 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
405 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
427 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
438 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
468 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
482 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
489 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
515 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
621 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/
H A Darith.ll23 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
35 ; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
59 ; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
96 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
132 ; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
169 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
205 ; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
242 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
278 ; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
315 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
H A Dcontrol-flow.ll21 ; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: br label %loop
27 ; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %res
32 ; CHECK-V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: br label %loop
38 ; CHECK-V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %res
43 ; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: br label %loop
49 ; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %res
54 ; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: br label %loop
60 ; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %res
71 ; CHECK-T1-LATENCY-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %res
183 ; CHECK-T1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %res
[all …]
H A Dload_store.ll38 ; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
64 ; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
90 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
116 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
142 ; CHECK-V8-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
168 ; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
225 ; CHECK-NOVEC-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
251 ; CHECK-FP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
277 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
303 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
H A Dcast.ll408 ; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
802 ; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
1984 ; CHECK-V8R-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
2378 ; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
3560 ; CHECK-V8R-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
3683 ; Vector cast cost of instructions lowering the cast to the stack.
4010 ; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
4021 ; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
4054 ; CHECK-V8R-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
4065 ; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AMDGPU/
H A Dshifts.ll30 ; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
53 ; SLOW64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
76 ; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
99 ; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
146 ; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
169 ; SLOW64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
192 ; FAST64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
215 ; SLOW64-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
262 ; FAST64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
285 ; SLOW64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
[all …]
H A Dfdiv.ll24 ; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
34 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
55 ; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
65 ; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
116 ; FP16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
124 ; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
132 ; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
159 ; NOFP16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
169 ; FP16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
220 ; FP16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
[all …]
H A Dbit-ops.ll26 ; SLOW16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
45 ; FAST16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
64 ; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
83 ; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
122 ; SLOW16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
141 ; FAST16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
160 ; SLOW16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
179 ; FAST16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
218 ; SLOW16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
237 ; FAST16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
[all …]
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllvm-bcanalyzer.rst18 version of the bitcode file. This tool is probably not of much interest or
78 Size. This is the size of the definitions of all types in the bitcode file.
110 The size, in bytes, of the list of dependent libraries in the module. Percentage
116 The total number of blocks of any kind in the bitcode file.
128 The total number of constants (of any type) defined in the Constant Pool.
183 The average size of a Value definition (of any type). This is computed by
184 dividing File Size by the total number of values of any type.
195 **# of VBR 32-bit Integers**
200 **# of VBR 64-bit Integers**
205 **# of VBR Compressed Bytes**
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dscalar-cmp-cmp-log-sel.ll5 ; TODO: add more tests for differing operand types of the two compares.
16 ; CHECK: cost of 3 for instruction: %cmp0 = icmp eq i8 %val1, %val2
17 ; CHECK: cost of 3 for instruction: %cmp1 = icmp eq i8 %val3, %val4
18 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
33 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
48 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
63 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
78 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
93 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
108 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
[all …]

12345678910>>...244