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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-p9-f128.ll11 %0 = call fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128 %a)
18 declare fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128)
43 declare fp128 @llvm.ppc.fmaf128.round.to.odd(fp128, fp128, fp128)
47 %0 = call fp128 @llvm.ppc.addf128.round.to.odd(fp128 %a, fp128 %b)
54 declare fp128 @llvm.ppc.addf128.round.to.odd(fp128, fp128)
58 %0 = call fp128 @llvm.ppc.subf128.round.to.odd(fp128 %a, fp128 %b)
66 declare fp128 @llvm.ppc.subf128.round.to.odd(fp128, fp128)
79 declare fp128 @llvm.ppc.mulf128.round.to.odd(fp128, fp128)
90 declare fp128 @llvm.ppc.divf128.round.to.odd(fp128, fp128)
94 %0 = call double @llvm.ppc.truncf128.round.to.odd(fp128 %a)
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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dupdate-module-level-options.s6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
H A Dset-oddspreg-nooddspreg-error.s6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
H A Dnooddspreg-error.s9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
/llvm-project-15.0.7/libcxx/test/std/library/description/conventions/customization.point.object/
H A Dniebloid.compile.pass.cpp56 auto odd = [](int x) { return x % 2 != 0; }; in __anond6f594150102() variable
64 static_assert(test(std::ranges::all_of, a, odd));
65 static_assert(test(std::ranges::any_of, a, odd));
70 static_assert(test(std::ranges::copy_if, a, a, odd));
73 static_assert(test(std::ranges::count_if, a, odd));
82 static_assert(test(std::ranges::find_if, a, odd));
83 static_assert(test(std::ranges::find_if_not, a, odd));
84 static_assert(test(std::ranges::for_each, a, odd));
110 static_assert(test(std::ranges::none_of, a, odd));
114 static_assert(test(std::ranges::partition, a, odd));
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/llvm-project-15.0.7/llvm/test/Transforms/PGOProfile/
H A Dcspgo_profile_summary.ll11 @odd = common dso_local global i32 0, align 4
30 %0 = load i32, ptr @odd, align 4
32 store i32 %inc, ptr @odd, align 4
69 ; PGOSUMMARY: %even.odd = select i1 %tobool{{[0-9]*}}, ptr @even, ptr @odd
72 ; CSPGOSUMMARY: %even.odd = select i1 %tobool{{[0-9]*}}, ptr @even, ptr @odd
105 ; CSPGOSUMMARY: %even.odd.i = select i1 %tobool.i{{[0-9]*}}, ptr @even, ptr @odd
107 ; CSPGOSUMMARY: %even.odd.i2 = select i1 %tobool.i{{[0-9]*}}, ptr @even, ptr @odd
115 %0 = load i32, ptr @odd, align 4
117 store i32 %inc, ptr @odd, align 4
/llvm-project-15.0.7/clang/test/Analysis/
H A DNewDelete-path-notes.cpp29 void test(Odd *odd) { in test() argument
30 odd->kill(); // expected-note{{Calling 'Odd::kill'}} in test()
32 delete odd; // expected-warning {{Attempt to free released memory}} in test()
H A Dstl-algorithm-modeling-aggressive-std-find-modeling.cpp58 bool odd(int i) { return i % 2; } in odd() function
64 const auto i3 = std::find_if(i1, i2, odd); in test_find_if1()
85 const auto i3 = std::find_if(std::execution::sequenced_policy(), i1, i2, odd); in test_find_if2()
106 const auto i3 = std::find_if_not(i1, i2, odd); in test_find_if_not1()
128 odd); in test_find_if_not2()
198 const auto i5 = std::find_first_of(i1, i2, i3, i4, odd); in test_find_first_of3()
222 i1, i2, i3, i4, odd); in test_find_first_of4()
292 const auto i5 = std::find_end(i1, i2, i3, i4, odd); in test_find_end3()
316 i1, i2, i3, i4, odd); in test_find_end4()
472 const auto i5 = std::search(i1, i2, i3, i4, odd); in test_search3()
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H A Dstl-algorithm-modeling.cpp53 bool odd(int i) { return i % 2; } in odd() function
59 const auto i3 = std::find_if(i1, i2, odd); in test_find_if1()
78 const auto i3 = std::find_if(std::execution::sequenced_policy(), i1, i2, odd); in test_find_if2()
97 const auto i3 = std::find_if_not(i1, i2, odd); in test_find_if_not1()
117 odd); in test_find_if_not2()
181 const auto i5 = std::find_first_of(i1, i2, i3, i4, odd); in test_find_first_of3()
203 i1, i2, i3, i4, odd); in test_find_first_of4()
267 const auto i5 = std::find_end(i1, i2, i3, i4, odd); in test_find_end3()
289 i1, i2, i3, i4, odd); in test_find_end4()
431 const auto i5 = std::search(i1, i2, i3, i4, odd); in test_search3()
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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll12 ; Force the float into an odd-numbered register using named registers and
19 ; The intention is that if odd single precision registers are permitted, the
23 ; On the other hand, if odd single precision registers are not permitted, it
46 ; Force the float into an odd-numbered register using named registers and
53 ; The intention is that if odd single precision registers are permitted, the
57 ; On the other hand, if odd single precision registers are not permitted, it
85 ; The intention is that if odd single precision registers are permitted, the
88 ; On the other hand, if odd single precision registers are not permitted, it
113 ; The intention is that if odd single precision registers are permitted, the
116 ; On the other hand, if odd single precision registers are not permitted, it
H A Dno-odd-spreg.ll22 ; The intention is that if odd single precision registers are permitted, the
25 ; On the other hand, if odd single precision registers are not permitted, it
52 ; -mno-odd-sp-reg doesn't need to affect double precision values so both cases
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/PowerPC/
H A Dstride-vectorization.ll19 %odd.idx = add nsw i64 %0, 1
22 %arrayidx.odd = getelementptr inbounds double, double* %b, i64 %odd.idx
25 %2 = load double, double* %arrayidx.odd, align 8
/llvm-project-15.0.7/libc/AOR_v20.02/math/
H A Dv_cosf.c46 v_u32_t odd, cmp; in V_NAME() local
53 odd = v_as_u32_f32 (n) << 31; in V_NAME()
70 y = v_as_f32_u32 (v_as_u32_f32 (y) ^ odd); in V_NAME()
H A Dv_sinf.c45 v_u32_t sign, odd, cmp; in V_NAME() local
53 odd = v_as_u32_f32 (n) << 31; in V_NAME()
69 y = v_as_f32_u32 (v_as_u32_f32 (y) ^ sign ^ odd); in V_NAME()
H A Dv_sin.c53 v_u64_t sign, odd, cmp; in V_NAME() local
61 odd = v_as_u64_f64 (n) << 63; in V_NAME()
80 y = v_as_f64_u64 (v_as_u64_f64 (y) ^ sign ^ odd); in V_NAME()
H A Dv_cos.c54 v_u64_t odd, cmp; in V_NAME() local
61 odd = v_as_u64_f64 (n) << 63; in V_NAME()
81 y = v_as_f64_u64 (v_as_u64_f64 (y) ^ odd); in V_NAME()
/llvm-project-15.0.7/llvm/test/Transforms/PGOProfile/Inputs/
H A Dthinlto_cspgo_bar_gen.ll4 @odd = common dso_local global i32 0, align 4
14 %0 = load i32, ptr @odd, align 4
16 store i32 %inc, ptr @odd, align 4
H A Dthinlto_cspgo_bar_use.ll4 @odd = common dso_local global i32 0, align 4
16 %0 = load i32, ptr @odd, align 4
18 store i32 %inc, ptr @odd, align 4
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dcmpxchg-lse-even-regs.ll5 ; doesn't allocate odd ones and that it can copy them around properly. N.b. we
6 ; don't actually check that they're sequential because FileCheck can't; odd/even
H A Darm64-extract.ll26 ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
38 ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
H A Dframelayout-unaligned-fp.ll3 ; The purpose of this test is to construct a scenario where an odd number
4 ; of callee-saved GPRs as well as an odd number of callee-saved FPRs are
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dpr25342.ll101 ; CHECK: odd.bb:
112 %ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %9, %odd.bb ]
113 %i.0 = phi i32 [ 0, %entry ], [ %inc, %odd.bb ]
131 br i1 %even, label %even.bb, label %odd.bb
137 br label %odd.bb
139 odd.bb:
/llvm-project-15.0.7/llvm/test/tools/gold/X86/Inputs/
H A Dthinlto_cspgo_bar.ll5 @odd = common dso_local local_unnamed_addr global i32 0, align 4
16 %0 = load i32, i32* @odd, align 4
18 store i32 %inc, i32* @odd, align 4
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dinlineasm-mve.ll36 define i32 @odd-GPR-constraint() {
38 ; CHECK-LABEL: odd-GPR-constraint
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dmsa-nooddspreg.ll3 ; Test that the register allocator honours +nooddspreg and does not pick an odd
38 ; Test that the register allocator hnours +noodspreg and does not pick an odd

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