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Searched refs:nv (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-nv-cond.s3 fcsel d28,d31,d31,nv
4 csel x0,x0,x0,nv
5 ccmp x0,x0,#0,nv
6 b.nv #0
H A Dbasic-a64-diagnostics.s1401 csetm x6, nv
1417 cinc x2, x0, nv
1430 cinv w8, x7, nv
/llvm-project-15.0.7/llvm/lib/Support/
H A Dregexec.c114 #define STATESETUP(m, nv) { (m)->space = malloc((nv)*(m)->g->nstates); \ argument
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/MachO/ARM/
H A Dit-nv.txt1 # RUN: llvm-objdump --macho -d %p/Inputs/it-nv.o | FileCheck %s
/llvm-project-15.0.7/lldb/test/API/types/
H A DAbstractBase.py207 nv = ("%s = '%s'" if quotedDisplay else "%s = %s") % (var, val)
209 substrs=[nv])
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A DV60-VDblNew.ll1 ; RUN: llc -march=hexagon -O2 -disable-vecdbl-nv-stores=0 < %s | FileCheck %s
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dassume2.ll59 %nv = xor i32 %v, -1
60 %cmp = icmp eq i32 %nv, 5
H A Dcanonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll153 define i1 @nv(i8 %x, i8 %y) {
154 ; CHECK-LABEL: @nv(
H A Dcanonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll163 define i1 @nv(i8 %x, i8 %y) {
164 ; CHECK-LABEL: @nv(
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dnew-value-check.s3 # RUN: not llvm-mc -triple=hexagon -relax-nv-checks < %s 2>&1 | \
/llvm-project-15.0.7/libcxx/test/support/
H A Dnasty_containers.h122 void swap(nasty_vector &nv) in swap() argument
128 { v_.swap(nv.v_); } in swap()
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUModifierSyntax.rst362 nv subsection
632 nv subsection
642 nv Indicates that instruction operates on
1033 nv subsection
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Neoverse/
H A DN2-basic-instructions.s419 csinv x3, xzr, xzr, nv
426 csinc w5, w6, w6, nv
435 csinv w9, w8, w8, nv
443 csinv w9, w8, w8, nv
1751 # CHECK-NEXT: 1 1 0.25 csinv x3, xzr, xzr, nv
1758 # CHECK-NEXT: 1 1 0.25 csinc w5, w6, w6, nv
1767 # CHECK-NEXT: 1 1 0.25 csinv w9, w8, w8, nv
1775 # CHECK-NEXT: 1 1 0.25 csinv w9, w8, w8, nv
2942 … - - - - - 0.25 0.25 0.25 0.25 - - csinc w5, w6, w6, nv
2951 … - - - - - 0.25 0.25 0.25 0.25 - - csinv w9, w8, w8, nv
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-basic-instructions.s419 csinv x3, xzr, xzr, nv
426 csinc w5, w6, w6, nv
435 csinv w9, w8, w8, nv
443 csinv w9, w8, w8, nv
1751 # CHECK-NEXT: 1 3 0.50 csinv x3, xzr, xzr, nv
1758 # CHECK-NEXT: 1 3 0.50 csinc w5, w6, w6, nv
1767 # CHECK-NEXT: 1 3 0.50 csinv w9, w8, w8, nv
1775 # CHECK-NEXT: 1 3 0.50 csinv w9, w8, w8, nv
2941 … 0.50 - - - - - - - - - - csinc w5, w6, w6, nv
2950 … 0.50 - - - - - - - - - - csinv w9, w8, w8, nv
[all …]
/llvm-project-15.0.7/clang/test/Analysis/
H A Dmisc-ps-region-store.m992 typedef struct rdar7813989_Val { rdar7813989_NestedVal nv; } rdar7813989_Val; field
996 int z = (x ? a->nv : b->nv).w;
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-instructions.txt953 # "cset w2, nv" and "csetm x3, al" are invalid aliases for these two
955 # CHECK: csinv x3, xzr, xzr, nv
969 # "cinc w5, w6, al" and "cinc x1, x2, nv" are invalid aliases for these two
970 # CHECK: csinc w5, w6, w6, nv
987 # "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two
989 # CHECK: csinv w9, w8, w8, nv
1005 # "cneg x4, x8, nv" and "cneg w5, w6, al" are invalid aliases for these two
1007 # CHECK: csinv w9, w8, w8, nv
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_sve.td1325 def SVCNTB : SInst<"svcntb", "nv", "", MergeNone, "aarch64_sve_cntb", [IsAppendSVALL, IsOverloadNon…
1326 def SVCNTH : SInst<"svcnth", "nv", "", MergeNone, "aarch64_sve_cnth", [IsAppendSVALL, IsOverloadNon…
1327 def SVCNTW : SInst<"svcntw", "nv", "", MergeNone, "aarch64_sve_cntw", [IsAppendSVALL, IsOverloadNon…
1328 def SVCNTD : SInst<"svcntd", "nv", "", MergeNone, "aarch64_sve_cntd", [IsAppendSVALL, IsOverloadNon…
/llvm-project-15.0.7/llvm/bindings/go/llvm/
H A Dir.go714 func (v Value) ReplaceAllUsesWith(nv Value) { C.LLVMReplaceAllUsesWith(v.C, nv.C) }
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64.td307 "nv", "HasNV", "true",
H A DAArch64InstrInfo.td66 AssemblerPredicateWithAll<(all_of FeatureNV), "nv">;
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_common_interceptors.inc2349 const struct __sanitizer_itimerval *nv =
2351 COMMON_INTERCEPTOR_READ_RANGE(ctx, &nv->it_interval.tv_sec,
2353 COMMON_INTERCEPTOR_READ_RANGE(ctx, &nv->it_interval.tv_usec,
2355 COMMON_INTERCEPTOR_READ_RANGE(ctx, &nv->it_value.tv_sec,
2357 COMMON_INTERCEPTOR_READ_RANGE(ctx, &nv->it_value.tv_usec,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td143 let Inst{55} = acc; // nv on GFX9+, TFE before. AccVGPR for data on GFX90A.