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/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-neg.s5 neg r15
6 neg r1
7 neg r22
8 neg r31
10 ; CHECK: neg r15 ; encoding: [0xf1,0x94]
11 ; CHECK: neg r1 ; encoding: [0x11,0x94]
12 ; CHECK: neg r22 ; encoding: [0x61,0x95]
15 ; CHECK-INST: neg r15
16 ; CHECK-INST: neg r1
17 ; CHECK-INST: neg r22
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcos-1.ll58 %neg = fneg double %x
78 %neg = fneg float %x
98 %neg = fneg float %x
122 %neg = fneg double %x
133 %neg = fneg double %x
155 %neg = fneg float %x
204 %neg = fneg double %x
229 %neg = fneg double %x
251 %neg = fneg double %x
297 %neg = fneg double %x
[all …]
H A Dnegated-bitmask.ll16 ret i8 %neg
29 ret i8 %neg
41 ret <4 x i32> %neg
53 ret <4 x i32> %neg
66 ret <4 x i32> %neg
81 ret i8 %neg
98 ret i32 %neg
113 ret i32 %neg
127 ret i8 %neg
138 ret i8 %neg
[all …]
H A Dsrem-canonicalize.ll10 %neg = sub nsw i32 0, %x
11 %srem = srem i32 %neg, %y
24 %neg = sub nsw i32 0, %x
25 %srem = srem i32 %y, %neg
35 %neg = sub i32 0, %x
36 %srem = srem i32 %neg, %y
46 %neg = sub nsw <2 x i32> <i32 0, i32 0>, %x
47 %srem = srem <2 x i32> %neg, %y
58 %neg = sub nsw i32 0, %x
59 %srem = srem i32 %neg, %y
[all …]
H A Dsub-lshr-or-to-icmp-select.ll12 %neg = sub i32 0, %x
13 %or = or i32 %neg, %x
28 %neg = sub i32 0, %x
29 %or = or i32 %x, %neg
43 %or = or <4 x i32> %neg, %x
57 %or = or <4 x i32> %x, %neg
72 %neg = sub i32 0, %x
73 %or = or i32 %neg, %x
75 store i32 %neg, i32* %p
89 %neg = sub i32 0, %x
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dnegate.ll8 %neg = sub nuw i32 0, %x
9 ret i32 %neg
17 ret <2 x i32> %neg
25 ret <2 x i32> %neg
33 %neg = sub nsw i8 0, %signbit
34 ret i8 %neg
43 ret <2 x i8> %neg
52 ret <2 x i8> %neg
61 %neg = sub i8 0, %signbit
62 ret i8 %neg
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dvop3-modifiers.s39 v_ceil_f16 v0, neg(0xabcd)
42 v_ceil_f16 v0, neg(abs(0xabcd))
57 v_ceil_f16 v0, neg(0xb118)
65 v_ceil_f16 v0, neg(0x3118)
69 v_ceil_f16_e64 v0, neg(0x3118)
78 v_ceil_f16_e64 v0, neg(|v1|)
89 v_ceil_f64 v[0:1], neg(1)
93 v_ceil_f64 v[0:1], neg(-1)
104 v_ceil_f64_e32 v[0:1], neg(1.0)
143 v_add_f32 v5, neg(0xbe22f983), v2
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Dneg.s12 neg z0.b, p0/m, z0.b label
18 neg z0.h, p0/m, z0.h label
24 neg z0.s, p0/m, z0.s label
30 neg z0.d, p0/m, z0.d label
36 neg z31.b, p7/m, z31.b label
42 neg z31.h, p7/m, z31.h label
48 neg z31.s, p7/m, z31.s label
54 neg z31.d, p7/m, z31.d label
70 neg z4.d, p7/m, z31.d label
82 neg z4.d, p7/m, z31.d label
H A Dneg-diagnostics.s4 neg z0.h, p0/m, z0.b label
10 neg z29.d, p7, z29.d label
18 neg z0.b, p8/m, z0.b label
23 neg z0.h, p8/m, z0.h label
28 neg z0.s, p8/m, z0.s label
33 neg z0.d, p8/m, z0.d label
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-neg-02.ll11 %neg = sub i32 0, %val
23 %neg = sub i32 0, %val
35 %neg = sub i32 0, %val
47 %neg = sub i32 0, %val
60 %neg = sub i64 0, %ext
75 %neg = sub i64 0, %ext
87 %neg = sub i64 0, %val
100 %neg = sub i64 0, %ashr
114 %neg = sub i64 0, %ashr
128 %neg = sub i64 0, %ashr
[all …]
H A Dint-abs-01.ll11 %neg = sub i32 0, %val
22 %neg = sub i32 0, %val
33 %neg = sub i32 0, %val
44 %neg = sub i32 0, %val
56 %neg = sub i64 0, %ext
69 %neg = sub i64 0, %ext
80 %neg = sub i64 0, %val
92 %neg = sub i64 0, %ashr
105 %neg = sub i64 0, %ashr
118 %neg = sub i64 0, %ashr
[all …]
H A Dvec-abs-02.ll11 %neg = sub <8 x i16> zeroinitializer, %val
22 %neg = sub <8 x i16> zeroinitializer, %val
33 %neg = sub <8 x i16> zeroinitializer, %val
44 %neg = sub <8 x i16> zeroinitializer, %val
57 %neg = sub <8 x i16> zeroinitializer, %val
70 %neg = sub <8 x i16> zeroinitializer, %val
82 %neg = sub <8 x i16> zeroinitializer, %val
94 %neg = sub <8 x i16> zeroinitializer, %val
106 %neg = sub <8 x i16> zeroinitializer, %val
119 %and1 = and <8 x i16> %shr, %neg
[all …]
H A Dvec-abs-04.ll11 %neg = sub <2 x i64> zeroinitializer, %val
22 %neg = sub <2 x i64> zeroinitializer, %val
33 %neg = sub <2 x i64> zeroinitializer, %val
44 %neg = sub <2 x i64> zeroinitializer, %val
57 %neg = sub <2 x i64> zeroinitializer, %val
70 %neg = sub <2 x i64> zeroinitializer, %val
82 %neg = sub <2 x i64> zeroinitializer, %val
94 %neg = sub <2 x i64> zeroinitializer, %val
106 %neg = sub <2 x i64> zeroinitializer, %val
118 %and1 = and <2 x i64> %shr, %neg
[all …]
H A Dvec-abs-03.ll11 %neg = sub <4 x i32> zeroinitializer, %val
22 %neg = sub <4 x i32> zeroinitializer, %val
33 %neg = sub <4 x i32> zeroinitializer, %val
44 %neg = sub <4 x i32> zeroinitializer, %val
57 %neg = sub <4 x i32> zeroinitializer, %val
70 %neg = sub <4 x i32> zeroinitializer, %val
82 %neg = sub <4 x i32> zeroinitializer, %val
94 %neg = sub <4 x i32> zeroinitializer, %val
106 %neg = sub <4 x i32> zeroinitializer, %val
118 %and1 = and <4 x i32> %shr, %neg
[all …]
H A Dvec-abs-01.ll11 %neg = sub <16 x i8> zeroinitializer, %val
22 %neg = sub <16 x i8> zeroinitializer, %val
33 %neg = sub <16 x i8> zeroinitializer, %val
44 %neg = sub <16 x i8> zeroinitializer, %val
57 %neg = sub <16 x i8> zeroinitializer, %val
70 %neg = sub <16 x i8> zeroinitializer, %val
82 %neg = sub <16 x i8> zeroinitializer, %val
94 %neg = sub <16 x i8> zeroinitializer, %val
106 %neg = sub <16 x i8> zeroinitializer, %val
120 %and1 = and <16 x i8> %shr, %neg
[all …]
H A Dint-neg-01.ll10 %neg = sub i32 0, %val
11 ret i32 %neg
20 %neg = sub i64 0, %ext
21 ret i64 %neg
31 %neg = sub i64 0, %ext
32 ret i64 %neg
40 %neg = sub i64 0, %val
41 ret i64 %neg
/llvm-project-15.0.7/clang/unittests/Analysis/FlowSensitive/
H A DSolverTest.cpp61 auto NotX = Ctx.neg(X); in TEST()
72 auto NotX = Ctx.neg(X); in TEST()
82 auto NotY = Ctx.neg(Y); in TEST()
94 auto NotX = Ctx.neg(X); in TEST()
126 auto NotX = Ctx.neg(X); in TEST()
145 auto NotX = Ctx.neg(X); in TEST()
165 auto NotX = Ctx.neg(X); in TEST()
167 auto NotY = Ctx.neg(Y); in TEST()
182 auto NotX = Ctx.neg(X); in TEST()
294 auto A = Ctx.iff(Ctx.neg(Ctx.disj(X, Y)), Ctx.conj(Ctx.neg(X), Ctx.neg(Y))); in TEST()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Drelocation-n64.s27 lui $3, %hi(%neg(%gp_rel(foo))) // RELOC: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 foo
32 addiu $2, $3, %lo(%neg(%gp_rel(foo))) // RELOC: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 foo
37 lui $3, %hi(%neg(%gp_rel(bar))) // RELOC: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 .data
42 addiu $2, $3, %lo(%neg(%gp_rel(bar))) // RELOC: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 .data
49 …lui $3, %hi(%neg(%gp_rel(foo))) // RELOC: R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI…
54 …addiu $2, $3, %lo(%neg(%gp_rel(foo))) // RELOC: R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO…
59 …lui $3, %hi(%neg(%gp_rel(bar))) // RELOC: R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI…
64 …addiu $2, $3, %lo(%neg(%gp_rel(bar))) // RELOC: R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO…
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Datomic64.ll28 ; MIPS4-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))
111 ; O1-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))
128 ; O2-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))
145 ; O3-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))
268 ; O1-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadSub)))
285 ; O2-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadSub)))
302 ; O3-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadSub)))
425 ; O1-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAnd)))
582 ; O1-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadOr)))
599 ; O2-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadOr)))
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dnegate.ll9 %neg = sub nuw i32 0, %x
10 ret i32 %neg
18 %neg = sub nuw <4 x i32> zeroinitializer, %x
19 ret <4 x i32> %neg
28 %neg = sub nsw i8 0, %signbit
29 ret i8 %neg
39 ret <4 x i32> %neg
50 %neg = sub i8 0, %signbit
51 ret i8 %neg
60 %neg = sub <4 x i32> zeroinitializer, %signbit
[all …]
H A Dmask-negated-bool.ll11 %neg = sub i32 0, %ext
12 %and = and i32 %neg, 1
22 %neg = sub i32 0, %ext
23 %and = and i32 %neg, 1
33 %neg = sub <4 x i32> zeroinitializer, %ext
34 %and = and <4 x i32> %neg, <i32 1, i32 1, i32 1, i32 1>
45 %neg = sub i32 0, %ext
46 %and = and i32 %neg, 1
56 %neg = sub i32 0, %ext
57 %and = and i32 %neg, 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsetcc-fneg-constant.ll20 %neg.mul = fsub float -0.0, %mul
108 %neg.a = fsub float -0.0, %a
121 %neg.a = fsub float -0.0, %a
134 %neg.a = fsub float -0.0, %a
147 %neg.a = fsub float -0.0, %a
160 %neg.a = fsub float -0.0, %a
173 %neg.a = fsub float -0.0, %a
186 %neg.a = fsub float -0.0, %a
199 %neg.a = fsub float -0.0, %a
212 %neg.a = fsub float -0.0, %a
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-bif-gen.ll13 %neg = xor <1 x i8> %C, <i8 -1>
14 %and = and <1 x i8> %neg, %B
28 %and = and <1 x i16> %neg, %B
42 %and = and <1 x i32> %neg, %B
56 %and = and <1 x i64> %neg, %B
68 %and = and <2 x i32> %neg, %B
80 %and = and <4 x i16> %neg, %B
92 %and = and <8 x i8> %neg, %B
106 %and = and <2 x i64> %neg, %B
118 %and = and <4 x i32> %neg, %B
[all …]
H A Daarch64-bit-gen.ll14 %neg = xor <1 x i8> %C, <i8 -1>
15 %and1 = and <1 x i8> %neg, %A
28 %neg = xor <1 x i16> %C, <i16 -1>
29 %and1 = and <1 x i16> %neg, %A
43 %and1 = and <1 x i32> %neg, %A
57 %and1 = and <1 x i64> %neg, %A
69 %and1 = and <2 x i32> %neg, %A
81 %and1 = and <4 x i16> %neg, %A
93 %and1 = and <8 x i8> %neg, %A
107 %and1 = and <2 x i64> %neg, %A
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dinsert-after-bundle.ll431 %neg = xor i32 %0, -1
434 %neg.1 = xor i32 %1, -1
437 %neg.2 = xor i32 %2, -1
440 %neg.3 = xor i32 %3, -1
443 %neg.4 = xor i32 %4, -1
446 %neg.5 = xor i32 %5, -1
449 %neg.6 = xor i32 %6, -1
452 %neg.7 = xor i32 %7, -1
455 %neg.8 = xor i32 %8, -1
458 %neg.9 = xor i32 %9, -1
[all …]

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