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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dmul.ll93 ; MIPS32-NEXT: multu $6, $3
122 ; MIPS32-NEXT: multu $6, $14
134 ; MIPS32-NEXT: multu $7, $14
136 ; MIPS32-NEXT: multu $6, $13
161 ; MIPS32-NEXT: multu $8, $14
163 ; MIPS32-NEXT: multu $7, $13
165 ; MIPS32-NEXT: multu $6, $12
185 ; MIPS32-NEXT: multu $4, $5
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmul-macro-variants.s95 # CHECK: multu $4, $5 # encoding: [0x00,0x85,0x00,0x19]
101 # CHECK-TRAP: multu $4, $5 # encoding: [0x00,0x85,0x00,0x19]
106 # CHECK: multu $5, $6 # encoding: [0x00,0xa6,0x00,0x19]
112 # CHECK-TRAP: multu $5, $6 # encoding: [0x00,0xa6,0x00,0x19]
H A Dmicromips-alu-instructions.s38 # CHECK-EL: multu $9, $7 # encoding: [0xe9,0x00,0x3c,0x9b]
81 # CHECK-EB: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c]
122 multu $9, $7
H A Dmips64-alu-instructions.s83 # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
108 multu $3,$5
H A Dmips-alu-instructions.s87 # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
112 multu $3,$5
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A D2008-08-01-AsmInline.ll8 ; CHECK: multu
11 …%asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwi…
H A Dmulll.ll13 ; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
H A Durem-seteq-illegal-types.ll153 ; MIPSEL-NEXT: multu $6, $1
156 ; MIPSEL-NEXT: multu $5, $1
161 ; MIPSEL-NEXT: multu $6, $9
H A Dmulull.ll14 ; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
H A Dconst-mult.ll236 ; MIPS32-NEXT: multu $4, $1
280 ; MIPS32-NEXT: multu $4, $1
324 ; MIPS32-NEXT: multu $4, $1
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1.s23 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
24 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips2.s29 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
30 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/MC/Mips/dsp/
H A Dvalid.s78 …multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0x…
80 …multu $4, $5 # CHECK: multu $4, $5 # encoding: [0x00,0x…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips1.s26 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
27 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips3.s22 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
23 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips2.s32 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
33 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips64.s43 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
44 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/MC/Mips/dspr2/
H A Dvalid.s106 …multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0x85,0…
108 …multu $4, $5 # CHECK: multu $4, $5 # encoding: [0x00,0x85,0…
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dmul.ll181 ; M2: multu $5, $7
187 ; 32R1-R5: multu $5, $7
210 ; MM32R3: multu $[[T0:[0-9]+]], $7
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips1/
H A Dvalid-mips1-el.txt73 0x19 0x00 0x9a 0x03 # CHECK: multu $gp, $26
74 0x19 0x00 0x32 0x01 # CHECK: multu $9, $18
H A Dvalid-mips1.txt28 0x01 0x32 0x00 0x19 # CHECK: multu $9, $18
39 0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips-dsp/
H A Dvalid.s35 multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/dsp/
H A Dvalid.txt76 0x00 0x85 0x10 0x19 # CHECK: multu $ac2, $4, $5
78 0x00 0x85 0x00 0x19 # CHECK: multu $4, $5
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips-dspr2/
H A Dvalid.s48 multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips2/
H A Dvalid-mips2-el.txt89 0x19 0x00 0x9a 0x03 # CHECK: multu $gp, $26
90 0x19 0x00 0x32 0x01 # CHECK: multu $9, $18

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