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/llvm-project-15.0.7/third-party/benchmark/src/
H A Dbenchmark_register.h16 int mult) { in AddPowers() argument
19 BM_CHECK_GE(mult, 2); in AddPowers()
26 for (T i = static_cast<T>(1); i <= hi; i *= mult) { in AddPowers()
32 if (i > kmax / mult) break; in AddPowers()
39 void AddNegatedPowers(std::vector<T>* dst, T lo, T hi, int mult) { in AddNegatedPowers() argument
52 const auto it = AddPowers(dst, hi_complement, lo_complement, mult); in AddNegatedPowers()
59 void AddRange(std::vector<T>* dst, T lo, T hi, int mult) { in AddRange() argument
64 BM_CHECK_GE(mult, 2); in AddRange()
86 AddNegatedPowers(dst, lo_inner, std::min(hi_inner, T{-1}), mult); in AddRange()
96 AddPowers(dst, std::max(lo_inner, T{1}), hi_inner, mult); in AddRange()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmul-constant-result.ll10 ; X86-LABEL: mult:
188 ; X64-HSW-LABEL: mult:
533 ; X86-NEXT: calll mult@PLT
542 ; X86-NEXT: calll mult@PLT
551 ; X86-NEXT: calll mult@PLT
561 ; X86-NEXT: calll mult@PLT
571 ; X86-NEXT: calll mult@PLT
581 ; X86-NEXT: calll mult@PLT
591 ; X86-NEXT: calll mult@PLT
601 ; X86-NEXT: calll mult@PLT
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmul-macro-variants.s21 # CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
24 # CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
28 # CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
31 # CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
35 # CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
38 # CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
42 # CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
45 # CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
49 # CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
52 # CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
[all …]
H A Dmicromips-alu-instructions.s37 # CHECK-EL: mult $9, $7 # encoding: [0xe9,0x00,0x3c,0x8b]
80 # CHECK-EB: mult $9, $7 # encoding: [0x00,0xe9,0x8b,0x3c]
121 mult $9, $7
H A Dmips64-alu-instructions.s82 # CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
107 mult $3,$5
H A Dmips-alu-instructions.s86 # CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
111 mult $3,$5
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dmul.ll34 ; M2: mult $4, $5
47 ; M4: mult $4, $5
73 ; M2: mult $4, $5
88 ; M4: mult $4, $5
114 ; M2: mult $4, $5
129 ; M4: mult $4, $5
155 ; M2: mult $4, $5
158 ; M4: mult $4, $5
177 ; M2: mult $4, $7
179 ; M2: mult $5, $6
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dmulll.ll15 ; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
17 ; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
H A Dmulull.ll16 ; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
18 ; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
H A Dmadd-msub.ll64 ; 16-NEXT: mult $5, $4
193 ; 16-NEXT: mult $5, $4
249 ; 16-NEXT: mult $4, $5
313 ; 16-NEXT: mult $5, $4
444 ; 16-NEXT: mult $5, $4
500 ; 16-NEXT: mult $4, $5
514 ; 32-NEXT: mult $5, $4
537 ; DSP-NEXT: mult $ac0, $5, $4
568 ; 16-NEXT: mult $5, $4
H A Dmul.ll12 ; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
H A Dmips64instrs.ll93 ; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
104 ; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfp16-no-condition.ll18 %mult = load half, half* %p2, align 2
19 %b = fmul half %a, %mult
41 %mult = load float, float* %p2, align 2
42 %b = fmul float %a, %mult
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dpr45525.ll24 %mult = mul i32 %single.pred, 3
28 %stored.value = phi i32 [ 7, %bb.1 ], [ %mult, %bb.2 ]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1.s21 …mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
22 …mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips2.s27 …mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
28 …mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/MC/Mips/dsp/
H A Dvalid.s77 …mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x…
79 …mult $2, $3 # CHECK: mult $2, $3 # encoding: [0x00,0x…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips1.s24 …mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
25 …mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips3.s20 …mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
21 …mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips2.s30 …mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
31 …mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips64.s41 …mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
42 …mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsARM.td1290 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1293 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1294 llvm_i32_ty /* mult op #2 (scalar) */, llvm_anyvector_ty /* pred */],
1297 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1302 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1303 llvm_i32_ty /* mult op #2 (scalar) */]>;
1305 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1306 llvm_i32_ty /* mult op #2 (scalar) */]>;
1308 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1311 [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
/llvm-project-15.0.7/llvm/test/MC/Mips/dspr2/
H A Dvalid.s105 …mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x43,0…
107 …mult $2, $3 # CHECK: mult $2, $3 # encoding: [0x00,0x43,0…
/llvm-project-15.0.7/llvm/test/Transforms/LowerMatrixIntrinsics/
H A Dtranspose-opts-iterator-invalidation.ll48 …%mult = call <2 x double> @llvm.matrix.multiply.v2f64.v4f64.v2f64(<4 x double> %a, <2 x double> %b…
52 %trans = call <2 x double> @llvm.matrix.transpose.v2f64(<2 x double> %mult, i32 2, i32 1)
/llvm-project-15.0.7/mlir/test/Dialect/AMX/
H A Dinvalid.mlir46 // expected-error@+1 {{'amx.tile_mulf' op bad mult shape: 4 x 4 x 4}}

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