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Searched refs:muls (Results 1 – 25 of 65) sorted by relevance

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/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-muls.s7 muls r22, r16
8 muls r19, r17
9 muls r28, r31
10 muls r31, r31
11 muls r16, r16
12 muls r16, r31
21 ; CHECK-INST: muls r22, r16
22 ; CHECK-INST: muls r19, r17
23 ; CHECK-INST: muls r28, r31
24 ; CHECK-INST: muls r31, r31
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vecreduce-mul.ll9 ; CHECK-NEXT: muls r0, r1, r0
20 ; CHECK-NEXT: muls r0, r1, r0
22 ; CHECK-NEXT: muls r1, r2, r1
23 ; CHECK-NEXT: muls r0, r1, r0
35 ; CHECK-NEXT: muls r0, r1, r0
37 ; CHECK-NEXT: muls r1, r2, r1
38 ; CHECK-NEXT: muls r0, r1, r0
49 ; CHECK-NEXT: muls r0, r1, r0
51 ; CHECK-NEXT: muls r1, r2, r1
52 ; CHECK-NEXT: muls r0, r1, r0
[all …]
H A Dthumb2-mla.ll13 ; NO_MULOPS: muls r0, r1, r0
24 ; NO_MULOPS: muls r0, r1, r0
H A Durem-seteq-illegal-types.ll9 ; CHECK-NEXT: muls r1, r0, r1
28 ; CHECK-NEXT: muls r0, r1, r0
46 ; CHECK-NEXT: muls r0, r1, r0
62 ; CHECK-NEXT: muls r1, r0, r1
H A Dschedm7-hazard.ll18 ; CHECK-NEXT: muls r0, r1, r0
27 ; NOBANK-NEXT: muls r0, r1, r0
/llvm-project-15.0.7/llvm/test/MC/VE/
H A DMUL.s14 # CHECK-INST: muls.w.sx %s11, 63, (60)1
16 muls.w.sx %s11, 63, (60)1
18 # CHECK-INST: muls.w.zx %s11, -64, %s22
20 muls.w.zx %s11, -64, %s22
22 # CHECK-INST: muls.l %s11, -64, (22)0
24 muls.l %s11, -64, (22)0
26 # CHECK-INST: muls.l.w %s11, -64, (22)0
28 muls.l.w %s11, -64, (22)0
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dmultiply.ll6 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
17 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
28 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
38 ; CHECK-NEXT: muls.l %s0, %s1, %s0
65 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
95 ; CHECK-NEXT: muls.l %s0, %s1, %s0
122 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
133 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
144 ; CHECK-NEXT: muls.w.sx %s0, 5, %s0
154 ; CHECK-NEXT: muls.l %s0, 5, %s0
[all …]
H A Drem.ll21 ; CHECK-NEXT: muls.l %s1, %s2, %s1
33 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
59 ; CHECK-NEXT: muls.l %s1, %s2, %s1
71 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
84 ; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
157 ; CHECK-NEXT: muls.l %s1, 3, %s1
169 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1
197 ; CHECK-NEXT: muls.l %s1, 3, %s1
209 ; CHECK-NEXT: muls.w.sx %s1, 3, %s1
239 ; CHECK-NEXT: muls.l %s0, %s0, %s1
[all …]
/llvm-project-15.0.7/llvm/test/MC/M68k/Arith/Classes/
H A DMxDiMu.s15 ; CHECK: muls %d1, %d0
17 muls %d1, %d0 label
21 ; CHECK: muls #0, %d0
23 muls #0, %d0 label
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Daddimm-mulimm.ll18 ; CHECK-THUMB-NEXT: muls r0, r1, r0
37 ; CHECK-THUMB-NEXT: muls r0, r1, r0
56 ; CHECK-THUMB-NEXT: muls r0, r1, r0
75 ; CHECK-THUMB-NEXT: muls r0, r1, r0
102 ; CHECK-THUMBV6M-NEXT: muls r1, r0, r1
141 ; CHECK-THUMBV6M-NEXT: muls r1, r0, r1
181 ; CHECK-THUMBV6M-NEXT: muls r1, r0, r1
193 ; CHECK-THUMBV7M-NEXT: muls r0, r1, r0
222 ; CHECK-THUMBV6M-NEXT: muls r1, r0, r1
234 ; CHECK-THUMBV7M-NEXT: muls r0, r1, r0
[all …]
H A Dmul_const.ll20 ; THUMB-NEXT: muls r0, r1, r0
41 ; THUMB-NEXT: muls r0, r1, r0
62 ; THUMB-NEXT: muls r0, r1, r0
83 ; THUMB-NEXT: muls r0, r1, r0
107 ; THUMB-NEXT: muls r0, r1, r0
131 ; THUMB-NEXT: muls r0, r1, r0
153 ; THUMB-NEXT: muls r0, r1, r0
177 ; THUMB-NEXT: muls r0, r1, r0
199 ; THUMB-NEXT: muls r0, r1, r0
224 ; THUMB-NEXT: muls r0, r1, r0
H A Dshifter_operand.ll71 ; CHECK-THUMB: muls r1, r2, r1
82 ; CHECK-THUMB: muls r1, r2, r1
94 ; CHECK-THUMB: muls r1, r2, r1
106 ; CHECK-THUMB: muls r1, r2, r1
118 ; CHECK-THUMB: muls r1, r2, r1
130 ; CHECK-THUMB: muls r1, r2, r1
142 ; CHECK-THUMB: muls r1, r2, r1
156 ; CHECK-THUMB: muls r1, r2, r1
170 ; CHECK-THUMB: muls r1, r2, r1
184 ; CHECK-THUMB: muls r1, r2, r1
[all …]
H A Dusub_sat_plus.ll16 ; CHECK-T1-NEXT: muls r1, r2, r1
26 ; CHECK-T2-NEXT: muls r1, r2, r1
106 ; CHECK-T1-NEXT: muls r1, r2, r1
117 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
126 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
145 ; CHECK-T1-NEXT: muls r1, r2, r1
156 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
165 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
184 ; CHECK-T1-NEXT: muls r1, r2, r1
196 ; CHECK-T2-NEXT: muls r1, r2, r1
H A Duadd_sat_plus.ll16 ; CHECK-T1-NEXT: muls r1, r2, r1
27 ; CHECK-T2-NEXT: muls r1, r2, r1
104 ; CHECK-T1-NEXT: muls r1, r2, r1
121 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
132 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
151 ; CHECK-T1-NEXT: muls r1, r2, r1
163 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
173 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
192 ; CHECK-T1-NEXT: muls r1, r2, r1
205 ; CHECK-T2-NEXT: muls r1, r2, r1
H A Davoid-cpsr-rmw.ll10 ; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2
12 ; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0
14 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
31 ; CHECK-NOT: muls
63 ; CHECK: muls r{{[0-9]+}}
64 ; CHECK: muls
H A Dssub_sat_plus.ll16 ; CHECK-T1-NEXT: muls r1, r2, r1
31 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
40 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
126 ; CHECK-T1-NEXT: muls r1, r2, r1
151 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
159 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
178 ; CHECK-T1-NEXT: muls r1, r2, r1
197 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
205 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
224 ; CHECK-T1-NEXT: muls r1, r2, r1
[all …]
H A Dsadd_sat_plus.ll16 ; CHECK-T1-NEXT: muls r1, r2, r1
39 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
126 ; CHECK-T1-NEXT: muls r1, r2, r1
151 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
159 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
178 ; CHECK-T1-NEXT: muls r1, r2, r1
197 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
205 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
224 ; CHECK-T1-NEXT: muls r1, r2, r1
244 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
[all …]
H A Dmemset-inline.ll44 ; CHECK-7A: muls [[REG:r[0-9]+]],
47 ; CHECK-6M-NOT: muls
70 ; CHECK-7A: muls [[REG:r[0-9]+]],
73 ; CHECK-6M: muls [[REG:r[0-9]+]],
H A Dgep-optimization.ll12 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
36 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
60 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
H A Dthumb1-div.ll29 ; CHECK-NEXT: muls
38 ; CHECK-NEXT: muls
H A Dcttz.ll44 ; CHECK-THUMB-NEXT: muls r0, r1, r0
93 ; CHECK-THUMB-NEXT: muls r0, r1, r0
141 ; CHECK-THUMB-NEXT: muls r0, r1, r0
197 ; CHECK-THUMB-NEXT: muls r2, r0, r2
215 ; CHECK-THUMB-NEXT: muls r2, r0, r2
260 ; CHECK-THUMB-NEXT: muls r0, r1, r0
302 ; CHECK-THUMB-NEXT: muls r0, r1, r0
345 ; CHECK-THUMB-NEXT: muls r0, r1, r0
398 ; CHECK-THUMB-NEXT: muls r2, r0, r2
416 ; CHECK-THUMB-NEXT: muls r2, r0, r2
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dhardware-mul.ll7 ; CHECK: muls r22, r24
16 ; CHECK: muls r22, r25
23 ; CHECK: muls r23, r24
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Durem-seteq-illegal-types.ll8 ; CHECK-NEXT: muls r1, r0, r1
33 ; CHECK-NEXT: muls r1, r0, r1
66 ; CHECK-NEXT: muls r1, r0, r1
87 ; CHECK-NEXT: muls r1, r0, r1
113 ; CHECK-NEXT: muls r3, r0, r3
133 ; CHECK-NEXT: muls r5, r1, r5
145 ; CHECK-NEXT: muls r5, r2, r5
H A Duxth.ll24 ; V6M-NEXT: muls r0, r1, r0
36 ; V6M-NEXT: muls r0, r1, r0
77 ; V6M-NEXT: muls r4, r3, r4
135 ; V6M-NEXT: muls r4, r3, r4
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmul-v4.s6 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0]
10 muls r0, r1, r2 label

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