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Searched refs:mayStore (Results 1 – 25 of 194) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatternsV65.td11 mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
21 mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
31 mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
45 mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
56 mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
67 mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
H A DHexagonVLIWPacketizer.cpp364 if (HII->isHVXVec(MI) && MI.mayStore()) in isNewifiable()
597 if (MI.getDesc().mayStore()) { in getPostIncrementOperand()
673 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
1114 if (MI.mayStore() && HII.isRestrictNoSlot1Store(MJ) && HII.isPureSlot0(MJ)) in cannotCoexistAsymm()
1126 if (HII.isNewValueStore(MI) && MJ.mayStore()) in cannotCoexistAsymm()
1302 bool StoreI = I.mayStore(), StoreJ = J.mayStore(); in hasDualStoreDependence()
1387 if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() || in isLegalToPacketizeTogether()
1529 bool LoadJ = J.mayLoad(), StoreJ = J.mayStore(); in isLegalToPacketizeTogether()
1530 bool LoadI = I.mayLoad(), StoreI = I.mayStore(); in isLegalToPacketizeTogether()
1701 if (MJ->mayStore() && !HII->isNewValueStore(*MJ)) in foundLSInPacket()
H A DHexagonOptAddrMode.cpp131 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI)) in INITIALIZE_PASS_DEPENDENCY()
134 if (MID.mayStore()) { in INITIALIZE_PASS_DEPENDENCY()
197 if ((!UseMID.mayLoad() && !UseMID.mayStore()) || in canRemoveAddasl()
203 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() && in canRemoveAddasl()
426 if ((!MID.mayLoad() && !MID.mayStore()) || in processAddUses()
521 if ((MID.mayLoad() || MID.mayStore())) { in analyzeUses()
725 } else if (UseMID.mayStore()) { in changeAddAsl()
753 else if (MID.mayStore()) in xformUseMI()
H A DHexagonVectorPrint.cpp117 if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) { in getInstrVecReg()
123 if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) { in getInstrVecReg()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td221 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
227 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
233 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
239 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
245 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
259 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
270 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
398 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
535 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
591 mayStore = 0 in
[all …]
H A DRISCVInstrInfoA.td18 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
33 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
165 let mayStore = 1;
189 let mayStore = 1;
200 let mayStore = 1;
210 let mayStore = 1;
264 let mayStore = 1;
293 let mayStore = 1;
H A DRISCVInstrInfoZicbo.td37 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
45 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
H A DRISCVInstrInfo.td484 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
523 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
529 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
536 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
545 hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
551 hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
557 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
564 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
605 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
710 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
[all …]
H A DRISCVInstrInfoVPseudos.td652 let mayStore = 0;
665 let mayStore = 0;
682 let mayStore = 0;
698 let mayStore = 0;
711 let mayStore = 0;
728 let mayStore = 0;
744 let mayStore = 0;
757 let mayStore = 0;
774 let mayStore = 0;
792 let mayStore = 0;
[all …]
H A DRISCVInstrInfoZk.td42 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
49 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
58 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp84 TempStream << (IIVDEntry.mayStore ? " * " : " "); in printView()
142 IIVDEntry.mayStore = MCDesc.mayStore(); in collectData()
153 {"mayStore", IIVD.mayStore}, in toJSON()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInsertHardClauses.cpp110 if (MI.mayLoad() || (MI.mayStore() && ST->shouldClusterStores())) { in getHardClauseType()
132 return MI.mayLoad() ? MI.mayStore() ? HARDCLAUSE_MIMG_ATOMIC in getHardClauseType()
137 return MI.mayLoad() ? MI.mayStore() ? HARDCLAUSE_VMEM_ATOMIC in getHardClauseType()
142 return MI.mayLoad() ? MI.mayStore() ? HARDCLAUSE_FLAT_ATOMIC in getHardClauseType()
H A DSIMemoryLegalizer.cpp753 if (!(MI->mayLoad() && !MI->mayStore())) in getLoadInfo()
767 if (!(!MI->mayLoad() && MI->mayStore())) in getStoreInfo()
814 if (!(MI->mayLoad() && MI->mayStore())) in getAtomicCmpxchgOrRmwInfo()
908 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
925 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1247 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
1277 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1547 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
1579 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1812 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
[all …]
H A DSIPostRABundler.cpp119 NextMI.mayLoad() == MI.mayLoad() && NextMI.mayStore() == MI.mayStore() && in canBundle()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrBulkMemory.td38 let mayStore = 1, hasSideEffects = 1 in
54 let mayLoad = 1, mayStore = 1 in
65 let mayStore = 1 in
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h67 if (MCID.mayStore())
84 if (MCID.mayStore())
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp334 if (!(PrevMI->mayStore() || PrevMI->mayLoad())) in areMemoryOpsAliased()
337 if (!(MI.mayStore() || PrevMI->mayStore())) in areMemoryOpsAliased()
342 return MI.mayStore() ? AR_WillAliasEverything : AR_MayAlias; in areMemoryOpsAliased()
344 return PrevMI->mayStore() ? AR_WillAliasEverything : AR_MayAlias; in areMemoryOpsAliased()
727 MI->mayStore() ? FaultMaps::FaultingLoadStore : FaultMaps::FaultingLoad; in insertFaultingInstr()
H A DRegAllocScore.cpp112 } else if (MI.mayLoad() && MI.mayStore()) { in calculateRegAllocScore()
116 } else if (MI.mayStore()) { in calculateRegAllocScore()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp306 if (Ldst->mayStore() && Ldst->getOperand(0).isReg()) { in canJoinInstructions()
406 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo()
410 if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() || in canHoistLoadStoreTo()
455 bool IsStore = Ldst.mayStore(); in changeToAddrMode()
484 if (!MI->mayLoad() && !MI->mayStore()) in processBasicBlock()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp33 if (MI->mayStore()) in hasRAWHazard()
186 if (!L0.mayLoad() || L0.mayStore() || L0.getNumMemOperands() != 1) in getHazardType()
258 if (!MI.mayLoad() || MI.mayStore() || MI.getNumMemOperands() != 1) in EmitInstruction()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsEVAInstrInfo.td80 bit mayStore = 1;
101 bit mayStore = 0;
117 bit mayStore = 1;
145 bit mayStore = 1;
H A DMipsDelaySlotFiller.cpp454 if (!MI.mayStore() && !MI.mayLoad()) in hasHazard()
463 SeenStore |= MI.mayStore(); in hasHazard()
476 if (MI.mayStore()) in hasHazard_()
502 HasHazard |= updateDefsUses(VT, MI.mayStore()); in hasHazard_()
507 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore); in hasHazard_()
511 SeenNoObjStore |= MI.mayStore(); in hasHazard_()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrSystem.td155 let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in
159 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
214 let mayStore = 1 in {
228 let mayLoad = 1, mayStore = 1, Defs = [CC] in
232 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
238 let mayLoad = 1, mayStore = 1, Uses = [R0L, R1L] in {
244 let mayLoad = 1, mayStore = 1, Uses = [R0L] in
248 let mayLoad = 1, mayStore = 1, Uses = [R0L], Defs = [CC] in
H A DSystemZInstrBuilder.h33 if (MCID.mayStore()) in addFrameReference()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp270 !MCID.mayStore())) in generateWaitCntInfo()
272 else if (MCID.mayStore()) in generateWaitCntInfo()
280 (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet))) in generateWaitCntInfo()

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