| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | PatternMatchTest.cpp | 81 bool match = mi_match(MIPtr, *MRI, m_GAdd(m_Reg(), m_Reg())); in TEST_F() 85 match = mi_match(MI, *MRI, m_GAdd(m_Reg(), m_Reg())); in TEST_F() 88 match = mi_match(MIBAdd, *MRI, m_GAdd(m_Reg(), m_Reg())); in TEST_F() 118 m_GAdd(m_Reg(Src0), m_Reg(Src1))); in TEST_F() 128 m_GMul(m_Reg(Src0), m_Reg(Src1))); in TEST_F() 135 m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2))); in TEST_F() 171 m_GFSub(m_Reg(Src0), m_Reg())); in TEST_F() 179 m_GAnd(m_Reg(Src0), m_Reg(Src1))); in TEST_F() 188 m_GOr(m_Reg(Src0), m_Reg(Src1))); in TEST_F() 197 m_GLShr(m_Reg(Src0), m_Reg(Src1))); in TEST_F() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPreLegalizerCombiner.cpp | 96 m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) { in matchClampI64ToI16() 98 m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16() 104 m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) { in matchClampI64ToI16() 106 m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) { in matchClampI64ToI16()
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| H A D | AMDGPUPostLegalizerCombiner.cpp | 93 m_GFCmp(m_Pred(Info.Pred), m_Reg(Info.LHS), m_Reg(Info.RHS)))) in matchFMinFMaxLegacy() 257 mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg))); in matchCvtF32UByteN() 261 bool IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt))); in matchCvtF32UByteN() 262 if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) { in matchCvtF32UByteN()
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| H A D | AMDGPUCombinerHelper.cpp | 268 if (!mi_match(Reg, MRI, m_GFNeg(m_Reg(Reg)))) in applyFoldableFneg() 277 if (mi_match(XReg, MRI, m_GFNeg(m_Reg(XReg)))) in applyFoldableFneg() 279 else if (mi_match(YReg, MRI, m_GFNeg(m_Reg(YReg)))) in applyFoldableFneg()
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| H A D | AMDGPURegBankCombiner.cpp | 143 MMMOpc.Min, m_CommutativeBinOp(MMMOpc.Max, m_Reg(Val), m_Cst(K0)), in matchMed() 146 MMMOpc.Max, m_CommutativeBinOp(MMMOpc.Min, m_Reg(Val), m_Cst(K1)), in matchMed()
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| H A D | AMDGPUInstructionSelector.cpp | 676 Src0, *MRI, m_OneUse(m_GLShr(m_Reg(ShiftSrc0), m_SpecificICst(16)))); in selectG_BUILD_VECTOR_TRUNC() 679 Src1, *MRI, m_OneUse(m_GLShr(m_Reg(ShiftSrc1), m_SpecificICst(16)))); in selectG_BUILD_VECTOR_TRUNC() 3240 if (mi_match(Reg, MRI, m_GZExt(m_Reg(ZExtSrc)))) in matchZeroExtendFromS32() 4404 if (mi_match(Reg, *MRI, m_GPtrAdd(m_Reg(BasePtr), m_Copy(m_ICst(Offset))))) { in selectMUBUFScratchOffset()
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| H A D | AMDGPURegisterBankInfo.cpp | 1794 if (mi_match(Reg, MRI, m_GAdd(m_Reg(Base), m_ICst(Const)))) in getBaseWithConstantOffset()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 68 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt() 84 m_all_of(m_MInstr(ExtMI), m_any_of(m_GAnyExt(m_Reg(ExtSrc)), in tryCombineAnyExt() 85 m_GSExt(m_Reg(ExtSrc)), in tryCombineAnyExt() 86 m_GZExt(m_Reg(ExtSrc)))))) { in tryCombineAnyExt() 124 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc))) || in tryCombineZExt() 125 mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) { in tryCombineZExt() 146 if (mi_match(SrcReg, MRI, m_GZExt(m_Reg(ZextSrc)))) { in tryCombineZExt() 184 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineSExt() 203 m_all_of(m_MInstr(ExtMI), m_any_of(m_GZExt(m_Reg(ExtSrc)), in tryCombineSExt() 316 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineTrunc() [all …]
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| H A D | MIPatternMatch.h | 252 inline operand_type_match m_Reg() { return operand_type_match(); } in m_Reg() function 351 inline bind_ty<Register> m_Reg(Register &R) { return R; }
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1633 !mi_match(LHS, MRI, m_GSExt(m_Reg(ExtSrc)))) in matchCombineShlOfExtend() 2273 mi_match(SrcReg, MRI, m_GShl(m_Reg(ShiftSrc), m_Reg(ShiftAmt))) && in matchCombineTruncOfShl() 2918 m_GXor(m_Reg(XorSrc), m_Reg(CstReg)))) in matchNotCmp() 3032 if (!mi_match(AndReg, MRI, m_GAnd(m_Reg(X), m_Reg(Y)))) { in matchXorOfAndWithSameReg() 3034 if (!mi_match(AndReg, MRI, m_GAnd(m_Reg(X), m_Reg(Y)))) in matchXorOfAndWithSameReg() 4049 m_GOr(m_GShl(m_Reg(ShlSrc), m_Reg(ShlAmt)), in matchOrShiftToFunnelShift() 4050 m_GLShr(m_Reg(LShrSrc), m_Reg(LShrAmt))))) in matchOrShiftToFunnelShift() 4986 if (mi_match(Dst, MRI, m_GFAdd(m_Reg(X), m_GFNeg(m_Reg(Y)))) && in matchRedundantNegOperands() 4991 else if (mi_match(Dst, MRI, m_GFSub(m_Reg(X), m_GFNeg(m_Reg(Y)))) && in matchRedundantNegOperands() 5001 mi_match(X, MRI, m_GFNeg(m_Reg(X))) && in matchRedundantNegOperands() [all …]
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| H A D | LoadStoreOpt.cpp | 85 if (!mi_match(Ptr, MRI, m_GPtrAdd(m_Reg(Info.BaseReg), m_Reg(PtrAddRHS)))) { in getPointerInfo() 208 m_GPtrAdd(m_Reg(BaseReg), m_ICst(Offset)))) { in instMayAlias()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 81 if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) || in matchICmpRedundantTrunc() 262 if (!mi_match(DefOp0->getParent(), MRI, m_GTrunc(m_Reg(Op0Wide))) || in tryToSimplifyUADDO() 263 !mi_match(DefOp1->getParent(), MRI, m_GTrunc(m_Reg(Op1Wide)))) in tryToSimplifyUADDO() 329 if (mi_match(U.getParent(), MRI, m_GZExt(m_Reg(WideReg)))) { in tryToSimplifyUADDO()
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| H A D | AArch64PostLegalizerCombiner.cpp | 282 m_any_of(m_GICmp(m_Pred(), m_Reg(), m_Reg()), in matchMutateAnyExtToZExt() 283 m_GFCmp(m_Pred(), m_Reg(), m_Reg()))); in matchMutateAnyExtToZExt()
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| H A D | AArch64InstructionSelector.cpp | 1116 if (mi_match(Reg, MRI, m_Neg(m_Reg(MatchReg)))) { in emitSelect() 1133 if (mi_match(Reg, MRI, m_Not(m_Reg(MatchReg)))) { in emitSelect() 1151 m_any_of(m_GAdd(m_Reg(MatchReg), m_SpecificICst(1)), in emitSelect() 1152 m_GPtrAdd(m_Reg(MatchReg), m_SpecificICst(1))))) { in emitSelect() 2070 if (!mi_match(I.getOperand(2).getReg(), MRI, m_Neg(m_Reg(NegatedReg)))) in convertPtrAddToAdd() 2247 m_OneNonDBGUse(m_GZExt(m_OneNonDBGUse(m_Reg(ZExt)))))) in earlySelect() 2296 m_GOr(m_OneNonDBGUse(m_GShl(m_Reg(ShiftSrc), m_ICst(ShiftImm))), in earlySelect() 2297 m_OneNonDBGUse(m_GAnd(m_Reg(MaskSrc), m_ICst(MaskImm)))))) in earlySelect()
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| H A D | AArch64PostLegalizerLowering.cpp | 962 if (!mi_match(DstReg, MRI, m_GTrunc(m_Reg(SrcReg)))) in matchFormTruncstore()
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| H A D | AArch64LegalizerInfo.cpp | 1064 if (mi_match(Root, MRI, m_GPtrAdd(m_Reg(NewBase), m_ICst(NewOffset))) && in matchLDPSTPAddrMode()
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