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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmicromips-loadstore-instructions.s66 # CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
125 # CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
161 lwp $16, 8($4)
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dinvalid.s102 lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
104 lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
105 …lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offs…
106 …lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
H A Dvalid.s278 lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] label
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/micromips-sizereduction/
H A Dmicromips-lwp-swp.ll22 ; CHECK-NEXT: lwp $16, 20($sp)
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsX86_64.def80 TARGET_BUILTIN(__builtin_ia32_lwpins64, "UcUOiUiIUi", "n", "lwp")
81 TARGET_BUILTIN(__builtin_ia32_lwpval64, "vUOiUiIUi", "n", "lwp")
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dlwp-intrinsics-x86_64.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64
H A Dlwp-intrinsics.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefixes=X86,X86_LWP
7 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64
H A Dstack-folding-lwp.ll2 ; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+lwp < %s | FileCheck %s
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dpr40514.ll57 …er,-avx512vnni,-avx512vpopcntdq,-pconfig,-clwb,-avx512f,-clzero,-pku,+mmx,-lwp,-rdpid,-xop,+rdseed…
/llvm-project-15.0.7/polly/test/ScheduleOptimizer/
H A Dpattern-matching-based-opts-after-delicm.ll66 …pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-clflushopt,-clwb,-clzero,-fma4,-lwp,-mwaitx,-pku,-prefe…
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips32r6/
H A Dinvalid.s218 lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
220 lwp $16, 8($34) # CHECK: :[[@LINE]]:14: error: invalid register number
221 …lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed…
222 …lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be dif…
H A Dvalid.s389 lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
/llvm-project-15.0.7/lldb/source/Plugins/Process/FreeBSD/
H A DNativeProcessFreeBSD.cpp957 for (lwpid_t lwp : lwp_ids) in ReinitializeThreads() local
958 AddThread(lwp); in ReinitializeThreads()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr23997.ll104 …s,-avx512er,-avx512vnni,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,-lwp,-rdpid,-xop,+rdseed…
H A Dpr54634.ll140 …t,-serialize,-tsxldtrk,-pconfig,-amx-bf16,-amx-tile,-amx-int8,-sse4a,-xop,-lwp,-fma4,-tbm,-mwaitx,…
/llvm-project-15.0.7/llvm/lib/Support/Unix/
H A DThreading.inc39 #include <lwp.h> // For _lwp_self()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DX86TargetParser.def169 X86_FEATURE (LWP, "lwp")
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r3/
H A Dvalid-el.txt184 0x04 0x22 0x08 0x10 # CHECK: lwp $16, 8($4)
H A Dvalid.txt184 0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dudiv.ll398 ; MMR3-NEXT: lwp $16, 36($sp)
H A Dsrem.ll398 ; MMR3-NEXT: lwp $16, 36($sp)
H A Dsdiv.ll446 ; MMR3-NEXT: lwp $16, 36($sp)
H A Durem.ll478 ; MMR3-NEXT: lwp $16, 36($sp)
H A Dxor.ll333 ; MM32R3-NEXT: lwp $2, 16($sp)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r6/
H A Dvalid.txt320 0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)

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