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Searched refs:lsrl (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/M68k/ShiftRotate/
H A Dlsr.ll32 define i32 @lsrl(i32 %a, i32 %b) nounwind {
33 ; CHECK-LABEL: lsrl:
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vmull-loop.ll19 ; CHECK-NEXT: lsrl r12, r5, #31
21 ; CHECK-NEXT: lsrl r4, r5, #31
24 ; CHECK-NEXT: lsrl r12, r5, #31
26 ; CHECK-NEXT: lsrl r4, r5, #31
H A Dshift_parts.ll107 ; CHECK-MVE-NEXT: lsrl r0, r1, #3
267 ; CHECK-MVE-NEXT: lsrl r0, r1, #3
284 ; CHECK-MVE-NEXT: lsrl r0, r1, #3
313 ; CHECK-MVE-NEXT: lsrl r0, r1, #31
330 ; CHECK-MVE-NEXT: lsrl r0, r1, #31
H A Dmve-vqshrn.ll312 ; CHECK-NEXT: lsrl r0, r1, #3
313 ; CHECK-NEXT: lsrl r2, r3, #3
341 ; CHECK-NEXT: lsrl r0, r1, #3
342 ; CHECK-NEXT: lsrl r2, r3, #3
H A Dmve-postinc-distribute.ll99 ; CHECK-NEXT: lsrl r10, r5, #6
104 ; CHECK-NEXT: lsrl r6, r5, #6
120 ; CHECK-NEXT: lsrl r12, r7, #6
121 ; CHECK-NEXT: lsrl r4, r11, #6
H A Dmve-laneinterleaving.ll201 ; CHECK-NEXT: lsrl r0, r1, #1
206 ; CHECK-NEXT: lsrl r2, r3, #1
217 ; CHECK-NEXT: lsrl r4, r3, #1
218 ; CHECK-NEXT: lsrl r0, r1, #1
H A Dmve-shifts.ll243 ; CHECK-NEXT: lsrl r0, r1, #4
244 ; CHECK-NEXT: lsrl r2, r3, #4
H A Dmve-satmul-loops.ll648 ; CHECK-NEXT: lsrl r4, r5, #31
655 ; CHECK-NEXT: lsrl r10, r5, #31
678 ; CHECK-NEXT: lsrl r0, r1, #31
800 ; CHECK-NEXT: lsrl r10, r5, #31
809 ; CHECK-NEXT: lsrl r4, r5, #31
816 ; CHECK-NEXT: lsrl r10, r5, #31
825 ; CHECK-NEXT: lsrl r4, r5, #31
848 ; CHECK-NEXT: lsrl r0, r1, #31
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/mve-intrinsics/
H A Dlongshift-demand.ll70 ; CHECK-NEXT: lsrl r0, r1, #3
151 ; CHECK-NEXT: lsrl r0, r1, #31
232 ; CHECK-NEXT: lsrl r0, r1, #32
409 ; CHECK-NEXT: lsrl r0, r1, #3
498 ; CHECK-NEXT: lsrl r0, r1, #31
587 ; CHECK-NEXT: lsrl r0, r1, #32
770 ; CHECK-NEXT: lsrl r0, r1, #3
859 ; CHECK-NEXT: lsrl r0, r1, #32
H A Dlongshift-const.ll323 ; CHECK-NEXT: lsrl r0, r1, #2
342 ; CHECK-NEXT: lsrl r0, r1, #32
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmve-scalar-shift.s102 # CHECK: lsrl lr, r1, #12 @ encoding: [0x5e,0xea,0x1f,0x31]
104 lsrl lr, r1, #12 label
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmve-scalar-shift.txt26 # CHECK: lsrl lr, r1, #12 @ encoding: [0x5e,0xea,0x1f,0x31]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dwhile-loops.ll212 ; CHECK-NEXT: lsrl r0, r11, #2
220 ; CHECK-NEXT: lsrl r6, r5, #2
228 ; CHECK-NEXT: lsrl r4, r1, #2
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrMVE.td580 def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,