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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dform-bitfield-extract-from-and.mir31 %lsb:_(s32) = G_CONSTANT i32 5
33 %shift:_(s32) = G_LSHR %x, %lsb
60 %lsb:_(s64) = G_CONSTANT i64 5
62 %shift:_(s64) = G_LSHR %x, %lsb
89 %lsb:_(s32) = G_CONSTANT i32 5
90 %shift:_(s32) = G_LSHR %x, %lsb
113 %lsb:_(s32) = G_CONSTANT i32 5
115 %shift:_(s32) = G_LSHR %x, %lsb
139 %lsb:_(s64) = G_CONSTANT i64 5
141 %shift:_(s64) = G_LSHR %x, %lsb
[all …]
H A Dform-bitfield-extract-from-sextinreg.mir17 ; CHECK: %lsb:_(s32) = G_CONSTANT i32 5
23 %lsb:_(s32) = G_CONSTANT i32 5
24 %shift:_(s32) = G_ASHR %x, %lsb
46 %lsb:_(s32) = G_CONSTANT i32 5
47 %shift:_(s32) = G_LSHR %x, %lsb
98 %lsb:_(s32) = G_CONSTANT i32 32
99 %shift:_(s32) = G_ASHR %x, %lsb
124 %lsb:_(s32) = G_CONSTANT i32 -1
125 %shift:_(s32) = G_ASHR %x, %lsb
148 %lsb:_(s32) = G_CONSTANT i32 1
[all …]
H A Dlegalize-ubfx.mir11 ; CHECK: %lsb:_(s32) = G_CONSTANT i32 1
13 ; CHECK: %ubfx:_(s32) = G_UBFX %copy, %lsb(s32), %width
16 %lsb:_(s32) = G_CONSTANT i32 1
18 %ubfx:_(s32) = G_UBFX %copy(s32), %lsb, %width
28 ; CHECK: %lsb:_(s64) = G_CONSTANT i64 1
30 ; CHECK: %ubfx:_(s64) = G_UBFX %copy, %lsb(s64), %width
33 %lsb:_(s64) = G_CONSTANT i64 1
35 %ubfx:_(s64) = G_UBFX %copy(s64), %lsb, %width
H A Dlegalize-sbfx.mir11 ; CHECK: %lsb:_(s32) = G_CONSTANT i32 1
13 ; CHECK: %sbfx:_(s32) = G_SBFX %copy, %lsb(s32), %width
16 %lsb:_(s32) = G_CONSTANT i32 1
18 %sbfx:_(s32) = G_SBFX %copy(s32), %lsb, %width
28 ; CHECK: %lsb:_(s64) = G_CONSTANT i64 1
30 ; CHECK: %sbfx:_(s64) = G_SBFX %copy, %lsb(s64), %width
33 %lsb:_(s64) = G_CONSTANT i64 1
35 %sbfx:_(s64) = G_SBFX %copy(s64), %lsb, %width
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/
H A Dbstrins_d.ll9 ;; R = or (and X, mask0), (and (shl Y, lsb), mask1)
11 ;; R = BSTRINS X, Y, msb, lsb
37 ;; R = or (and X, mask0), (shl (and Y, mask1), lsb)
39 ;; R = BSTRINS X, Y, msb, lsb
67 ;; R = BSTRINS X, (srl (and Y, mask1), lsb), msb, lsb
123 ;; R = BSTRINS X, (const >> lsb), msb, lsb
H A Dbstrins_w.ll9 ;; R = or (and X, mask0), (and (shl Y, lsb), mask1)
11 ;; R = BSTRINS X, Y, msb, lsb
37 ;; R = or (and X, mask0), (shl (and Y, mask1), lsb)
39 ;; R = BSTRINS X, Y, msb, lsb
67 ;; R = BSTRINS X, (srl (and Y, mask1), lsb), msb, lsb
135 ;; R = BSTRINS X, (const >> lsb), msb, lsb
H A Dmisc.mir87 # opcode{11-1} | msb |opcode{0}| lsb | rj | rd
115 # opcode | msb | lsb | rj | rd
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dstore-widen-negv.ll7 %lsb = getelementptr inbounds [4 x i8], [4 x i8]* %ptr, i32 0, i32 2
9 store i8 -120, i8* %lsb, align 2
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dbitfield-insert-0.ll3 ; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one
4 ; point, in the edge case where lsb = 0. Just make sure.
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A Dgfx7_soffset_1bad09.rst15 * If offset is specified as a register, it supplies an unsigned byte offset but 2 lsb's are ignored.
16 …f:`uimm32<amdgpu_synid_uimm32>`, it supplies a 32-bit unsigned byte offset but 2 lsb's are ignored.
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td408 bits<5> lsb;
409 let Inst{25 - 21} = lsb; // lsb
422 bits<5> lsb;
427 let Inst{4 - 0} = lsb;
432 class I_5_XZ_U2<bits<6> sop, bits<5> lsb, bits<5> msb, dag outs, dag ins,
437 let Inst{25 - 21} = lsb; // lsb
456 let Inst{4 - 0} = size_lsb{4 - 0}; // lsb
460 class I_5_XZ_US<bits<6> sop, bits<5> lsb, bits<5> msb, string op,
462 : I_5_XZ_U2<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
465 class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
[all …]
/llvm-project-15.0.7/libc/src/__support/FPUtil/generic/
H A Dsqrt_80_bit_long_double.h102 bool lsb = y & 1; // Least significant bit in sqrt() local
119 if (rb && (lsb || (r != 0))) in sqrt()
H A Dsqrt.h139 bool lsb = y & 1; // Least significant bit
156 if (rb && (lsb || (r != 0)))
/llvm-project-15.0.7/lldb/test/Shell/Minidump/
H A Ddump-all.test25 # RUN: %lldb -c %t -o 'process plugin dump --lsb-release' | FileCheck --check-prefix=CHECKLSB %s
81 /etc/lsb-release output
83 # CHECKLSB: /etc/lsb-release:
84 # CHECKLSB-NEXT: /etc/lsb-release output
/llvm-project-15.0.7/mlir/lib/ExecutionEngine/
H A DFloat16bits.cpp119 uint32_t lsb = (floatBits.u >> kF32BfMantiBitDiff) & 1; in float2bfloat() local
120 uint32_t roundingBias = 0x7fff + lsb; in float2bfloat()
/llvm-project-15.0.7/libc/src/__support/FPUtil/
H A DHypot.h218 bool lsb = y_new & UIntType(2);
234 if (round_bit && (lsb || sticky_bits || (r != 0)))
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dglobal-variable-big.ll9 ; (lsb) 0x0102'0304'0506...0F10 (msb)
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp122 uint64_t msb = N.getConstantOperandVal(1), lsb = N.getConstantOperandVal(2); in selectShiftMask() local
123 if (lsb == 0 && Log2_32(ShiftWidth) <= msb + 1) { in selectShiftMask()
H A DLoongArchISelLowering.cpp413 uint64_t lsb, msb; in performANDCombine() local
434 lsb = CN->getZExtValue(); in performANDCombine()
438 if (SMIdx != 0 || lsb + SMLen > ValTy.getSizeInBits()) in performANDCombine()
456 lsb = 0; in performANDCombine()
459 msb = lsb + SMLen - 1; in performANDCombine()
462 DAG.getConstant(lsb, DL, GRLenVT)); in performANDCombine()
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/
H A Dinvalid64.s71 # CHECK: :[[#@LINE+1]]:21: error: msb is less than lsb
75 # CHECK: :[[#@LINE+1]]:22: error: msb is less than lsb
H A Dinvalid.s185 # CHECK: :[[#@LINE+1]]:21: error: msb is less than lsb
189 # CHECK: :[[#@LINE+1]]:22: error: msb is less than lsb
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfast-isel-select.ll6 ; lsb is zero.
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrFormats.td416 // opcode Rd addr 5msb's address 16 lsb's
430 bits<16> lsb;
437 let Inst{15 - 0} = lsb;
447 // opcode Rd const 5msb's constant 16 lsb's
458 bits<16> lsb;
465 let Inst{15 - 0} = lsb;
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_rtl_amd64.S70 shr $4, %rsp # clear 4 lsb, align to 16
188 shr $4, %rsp # clear 4 lsb, align to 16
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZOperands.td176 // Bits 0-15 (counting from the lsb).
182 // Bits 16-31 (counting from the lsb).
188 // Bits 32-47 (counting from the lsb).
194 // Bits 48-63 (counting from the lsb).

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