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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumbv8.1m.s183 wls lr, r2, #0
188 dls lr, r2
193 le lr, .Lstart
203 dls lr, lr
208 dls lr, r0
213 dls lr, r1
763 wls lr, lr, #1192
768 wls lr, lr, #2134
773 wls lr, lr, #962
988 le lr, #-1
[all …]
H A Dmve-misc.s29 # CHECK: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd]
31 wlstp.64 lr, lr, #3026
111 dlstp.8 lr, r5
115 dlstp.16 lr, r5
119 dlstp.32 lr, r7
123 dlstp.64 lr, r2
139 letp lr, #-2
143 letp lr, #-8
147 letp lr, #-4094
155 letp lr, #8
[all …]
H A Dmve-scalar-shift.s17 asrl lr, r1, #27
22 asrleq lr, r1, #27
56 cinc lr, r7, pl
60 cinv lr, r12, hs
72 cset lr, eq
76 csetm lr, hs
100 lsll lr, r1, r4
108 sqrshr lr, r12
124 sqshl lr, #17
132 srshr lr, #11
[all …]
H A Dmve-reductions.s27 vaddv.s16 lr, q0
40 vaddva.s16 lr, q0
46 vaddvat.s16 lr, q0
47 vaddvae.s16 lr, q0
62 vminv.s8 lr, q0
65 vminv.s16 lr, q0
68 vminv.s32 lr, q2
83 vminav.s32 lr, q1
86 vmaxv.s8 lr, q4
89 vmaxv.s16 lr, q0
[all …]
H A Dseh-packed.s543 bx lr
557 bx lr
571 bx lr
617 bx lr
753 bx lr
783 bx lr
803 bx lr
823 bx lr
887 bx lr
901 bx lr
[all …]
H A Dmve-reductions-fp.s7 # CHECK: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
10 vminnmv.f16 lr, q3
12 # CHECK: vminnmv.f32 lr, q1 @ encoding: [0xee,0xee,0x82,0xef]
15 vminnmv.f32 lr, q1
17 # CHECK: vminnmav.f16 lr, q0 @ encoding: [0xec,0xfe,0x80,0xef]
20 vminnmav.f16 lr, q0
25 vminnmav.f32 lr, q3
30 vmaxnmv.f16 lr, q1
45 vmaxnmav.f32 lr, q7
57 vminnmavt.f32 lr, q3
[all …]
H A Dseh.s191 push {r4-r8,lr}
193 push {r4-r7,lr}
197 push {r3-r7,lr}
203 mov lr, sp
204 .seh_save_sp lr
211 push {r3-r7,lr}
230 bx lr
255 push {r4-r5,lr}
286 push {r4-r5,lr}
306 bx lr
[all …]
H A Dseh-epilog-sharing.s107 push.w {r4-r7,lr}
108 .seh_save_regs_w {r4-r7,lr}
120 bx lr
130 bx lr
142 bxge lr
149 push.w {r4-r7,lr}
150 .seh_save_regs_w {r4-r7,lr}
165 pop.w {r4-r7,lr}
175 pop.w {r4-r7,lr}
184 pop.w {r4-r7,lr}
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfloat-helpers.s46 ; CHECK-SOFT-NEXT: mov pc, lr
53 ; CHECK-SOFTFP-NEXT: mov pc, lr
69 ; CHECK-SOFT-NEXT: mov pc, lr
92 ; CHECK-SOFT-NEXT: mov pc, lr
115 ; CHECK-SOFT-NEXT: mov pc, lr
140 ; CHECK-SOFT-NEXT: mov pc, lr
171 ; CHECK-SOFT-NEXT: mov pc, lr
202 ; CHECK-SOFT-NEXT: mov pc, lr
233 ; CHECK-SOFT-NEXT: mov pc, lr
264 ; CHECK-SOFT-NEXT: mov pc, lr
[all …]
H A D2011-02-04-AntidepMultidef.ll27 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
30 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
41 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
44 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
55 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
58 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
69 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
72 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
80 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
83 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
[all …]
H A Dmachine-outliner-lr-regsave.mir20 ; CHECK: liveins: $lr
25 ; CHECK: liveins: $lr
30 ; CHECK: liveins: $lr
44 liveins: $lr
52 liveins: $lr
60 liveins: $lr
76 liveins: $lr
111 liveins: $lr
119 liveins: $lr
127 liveins: $lr
[all …]
H A Dmachine-outliner-default.mir20 ; CHECK: liveins: $lr
25 ; CHECK: liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11
39 liveins: $lr
47 liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11
55 liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11
63 liveins: $lr, $r6, $r7, $r8, $r9, $r10, $r11
64 $r2 = MOVr $lr, 14, $noreg, $noreg
74 ; CHECK: liveins: $lr
90 ; CHECK: $r2 = tMOVr $lr, 14 /* CC::al */, $noreg
93 liveins: $lr
[all …]
H A Dmachine-outliner-calls.mir24 ; CHECK: liveins: $r4, $lr
42 BL @bar, implicit-def dead $lr, implicit $sp
49 BL @bar, implicit-def dead $lr, implicit $sp
56 BL @bar, implicit-def dead $lr, implicit $sp
63 BL @bar, implicit-def dead $lr, implicit $sp
70 BL @bar, implicit-def dead $lr, implicit $sp
86 ; CHECK: liveins: $r7, $lr
137 ; CHECK: liveins: $r4, $lr
153 BL @bar, implicit-def dead $lr, implicit $sp
194 ; CHECK: liveins: $r7, $lr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dldm-stm-postinc.ll9 br i1 %1, label %._crit_edge, label %.lr.ph
11 .lr.ph: ; preds = %.lr.ph, %0
12 %i.02 = phi i32 [ %3, %.lr.ph ], [ 0, %0 ]
13 %.01 = phi i32* [ %4, %.lr.ph ], [ %a, %0 ]
18 br i1 %5, label %._crit_edge, label %.lr.ph
29 br i1 %1, label %._crit_edge, label %.lr.ph
31 .lr.ph: ; preds = %.lr.ph, %0
32 %i.02 = phi i32 [ %3, %.lr.ph ], [ 0, %0 ]
51 .lr.ph: ; preds = %.lr.ph, %0
70 .lr.ph: ; preds = %.lr.ph, %0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/
H A Datomics.ll11 ; OPT: br label %.lr.ph
12 ; OPT: .lr.ph:
27 br label %.lr.ph
35 .lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
54 ; OPT: .lr.ph:
66 br label %.lr.ph
74 .lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
95 ; OPT: .lr.ph:
116 .lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
134 ; OPT: .lr.ph:
[all …]
H A Ddifferent-addrspace-addressing-mode-loops.ll11 ; OPT: br label %.lr.ph
12 ; OPT: {{^}}.lr.ph:
22 br label %.lr.ph
30 .lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
51 ; OPT: {{^}}.lr.ph:
60 br label %.lr.ph
68 .lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
88 ; OPT: {{^}}.lr.ph
98 br label %.lr.ph
106 .lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmve-lol.txt8 # CHECK: wls lr, r3, 0xc <$t.0+0xc> @ imm = #8
12 wls lr, r3, #8
14 le lr, #-8
21 wlstp.8 lr, r3, #8
23 letp lr, #-8
30 wlstp.16 lr, r3, #8
32 letp lr, #-8
39 wlstp.32 lr, r3, #8
41 letp lr, #-8
48 wlstp.64 lr, r3, #8
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-returnaddress-liveins.mir20 ; CHECK: liveins: $w0, $x0, $lr
23 ; CHECK: $lr = COPY [[COPY]]
24 ; CHECK: XPACLRI implicit-def $lr, implicit $lr
52 ; CHECK: $lr = COPY [[COPY]]
53 ; CHECK: XPACLRI implicit-def $lr, implicit $lr
60 liveins: $w0, $x0, $lr
82 ; CHECK: $lr = COPY [[COPY]]
83 ; CHECK: XPACLRI implicit-def $lr, implicit $lr
87 ; CHECK: $lr = COPY [[COPY]]
88 ; CHECK: XPACLRI implicit-def $lr, implicit $lr
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ARM/
H A Darm-unroll.ll18 br i1 %1, label %.lr.ph, label %._crit_edge
20 .lr.ph: ; preds = %0, %.lr.ph
21 %i.02 = phi i32 [ %5, %.lr.ph ], [ 0, %0 ]
22 %sum.01 = phi i32 [ %4, %.lr.ph ], [ 0, %0 ]
41 br i1 %1, label %.lr.ph, label %._crit_edge
43 .lr.ph:
44 %i.02 = phi i32 [ %5, %.lr.ph ], [ 0, %0 ]
45 %sum.01 = phi i32 [ %4, %.lr.ph ], [ 0, %0 ]
46 %sum.02 = phi i32 [ %6, %.lr.ph ], [ 0, %0 ]
47 %sum.03 = phi i32 [ %7, %.lr.ph ], [ 0, %0 ]
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/COFF/
H A Darm-unwind-packed.s508 bx lr
514 bx lr
520 bx lr
541 bx lr
602 bx lr
615 bx lr
624 bx lr
633 bx lr
667 bx lr
673 bx lr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmachine-outliner-noreturn-save-lr.mir26 liveins: $lr
28 ; CHECK: liveins: $lr
29 ; CHECK: $x0 = ORRXrs $xzr, $lr, 0
31 ; CHECK: $lr = ORRXrs $xzr, $x0, 0
48 liveins: $lr
50 ; CHECK: liveins: $lr
51 ; CHECK: $x0 = ORRXrs $xzr, $lr, 0
70 liveins: $lr
72 ; CHECK: liveins: $lr
92 liveins: $lr
[all …]
H A Dexpand-blr-rvmarker-pseudo.mir37 …ECK-NEXT: BLR $x0, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, …
41 # CHECK-NEXT: RET undef $lr, implicit killed $w0
49 liveins: $lr, $x0
64 # CHECK-NEXT: RET undef $lr, implicit killed $w0
69 liveins: $lr, $x0
84 # CHECK-NEXT: RET undef $lr
89 liveins: $lr, $x0, $x1, $x2
104 # CHECK-NEXT: RET undef $lr, implicit killed $w0
109 liveins: $lr, $w0, $w1
125 # CHECK-NEXT: RET undef $lr, implicit killed $w0
[all …]
H A Dcfi-fixup.mir94 ; CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
158 liveins: $w0, $lr, $x18
164 liveins: $w0, $lr, $x18
168 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
206 frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
321 liveins: $w0, $lr, $x18
327 liveins: $w0, $lr, $x18
331 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
362 frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
486 frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Difcvt-cbz.mir41 liveins: $r0, $lr, $r7
47 liveins: $r7, $lr
59 liveins: $lr, $r7
84 ; CHECK: liveins: $r7, $lr
94 ; CHECK: liveins: $lr, $r7
98 liveins: $r0, $lr, $r7
104 liveins: $r7, $lr
116 liveins: $lr, $r7
156 liveins: $r0, $lr, $r7
163 liveins: $r7, $lr
[all …]
/llvm-project-15.0.7/lld/test/ELF/
H A Darm-exidx-dedup.s35 bx lr
44 bx lr
54 bx lr
61 bx lr
70 bx lr
81 bx lr
89 bx lr
100 bx lr
112 bx lr
124 bx lr
[all …]

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