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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfmf-propagation.ll19 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_contract1:'
42 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_contract2:'
131 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast1:'
154 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast2:'
236 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast1:'
265 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast2:'
294 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn_ieee:'
432 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
542 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fcmp_nnan:'
546 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fcmp_nnan:'
[all …]
H A Dadd_cmp.ll12 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiUnsigned:entry'
25 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiSigned:entry'
38 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiUnsignedOverflow:entry'
51 ; CHECK: Optimized lowered selection DAG: %bb.0 'addiCmpiSignedOverflow:entry'
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dcombine_loads_from_build_pair.ll6 ; between "Initial selection DAG" and "Optimized lowered selection DAG".
18 ; CHECK-LABEL: Optimized lowered selection DAG:
H A Dlower-copy-undef-src.mir4 # copy rather than lowered into a target instruction with the undef flag
H A Dtwoaddr-sink.ll4 ; revisiting) an instruction that was lowered by TII->convertToThreeAddress()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dendcf-loop-header.ll4 ; loop block. This intrinsic will be lowered to s_or_b64 by the code
9 ; This is was lowered from the llvm.SI.end.cf intrinsic:
H A Dselect-undef.ll48 ; Make sure the vector undef isn't lowered into 0s.
87 ; Make sure the vector undef isn't lowered into 0s.
126 ; Make sure the vector undef isn't lowered into 0s.
165 ; Make sure the vector undef isn't lowered into 0s.
204 ; Make sure the vector undef isn't lowered into 0s.
H A Dicmp-select-sete-reverse-args.ll3 ;Test that a select with reversed True/False values is correctly lowered
/llvm-project-15.0.7/flang/include/flang/Parser/
H A Dcharacters.h69 std::string lowered{str}; in ToLowerCaseLetters()
70 for (char &ch : lowered) { in ToLowerCaseLetters()
73 return lowered; in ToLowerCaseLetters()
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/X86/
H A Dsqrt.ll21 ; We don't care about propagating 'tail' because this is not going to be a lowered as a call.
32 ; We don't change this because it will be lowered to a call that could
/llvm-project-15.0.7/flang/test/Lower/OpenACC/Todo/
H A Dacc-routine.f906 // CHECK: not yet implemented: OpenACC Routine construct not lowered yet!
/llvm-project-15.0.7/mlir/include/mlir/Dialect/AMX/
H A DAMX.td87 vector type of the result. This is eventually lowered into the
116 eventually lowered into the "tileloadd" instruction with the
147 eventually lowered into the "tilestored" instruction with the
181 pairs of "bf16"). The operation is eventually lowered into the
219 lowered into one of the "tdpbssd", "tdpbsud", "tdpbusd", or "tdpbuud"
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dfdeclare-opencl-builtins.cl19 // Test that Attr.Const from OpenCLBuiltins.td is lowered to a readnone attribute.
27 // Test that Attr.Pure from OpenCLBuiltins.td is lowered to a readonly attribute.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmacho-comdat.ll6 ; CHECK: LLVM ERROR: MachO doesn't support COMDATs, 'f' cannot be lowered.
H A Delf-group.ll1 ; Checks that comdat with nodeduplicate kind is lowered to a zero-flag ELF
H A Ddwarf_eh_resume.ll5 ; Check that 'resume' is lowered to _Unwind_Resume which marked as 'noreturn'
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Ddbg-value-frame-index-2.ll3 ; Test that stack frame dbg.values are lowered to DBG_VALUEs, in blocks that
9 ; independent of the order the instructions get lowered, but should not
/llvm-project-15.0.7/llvm/test/DebugInfo/PowerPC/
H A Dline.test5 ; branch, then further lowered to cmplwi + brcc but without the fidelity that
/llvm-project-15.0.7/llvm/test/DebugInfo/ARM/
H A Dline.test5 ; branch, then further lowered to CMPri + brcc but without the fidelity that
/llvm-project-15.0.7/mlir/lib/Conversion/AMDGPUToROCDL/
H A DAMDGPUToROCDL.cpp228 Operation *lowered = rewriter.create<Intrinsic>(loc, resultTypes, args, in matchAndRewrite() local
230 if (lowered->getNumResults() == 1) { in matchAndRewrite()
231 Value replacement = lowered->getResult(0); in matchAndRewrite()
/llvm-project-15.0.7/lld/test/wasm/lto/
H A Datomics.ll5 ; enabled because LLVM atomics will be lowered to regular ops.
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Vector/
H A Dexpand_single_elem_build_vec.ll4 ; Check that a single-element insertion is lowered to a insert_vector_elt node for isel.
/llvm-project-15.0.7/llvm/test/Transforms/Coroutines/
H A Dcoro-cleanup.ll1 ; Make sure that all library helper coro intrinsics are lowered.
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dsimd-nested-shuffles.ll4 ; lowered. Regression test for bug 39275.
/llvm-project-15.0.7/llvm/test/Transforms/LowerSwitch/
H A D2014-06-11-SwitchDefaultUnreachableOpt.ll3 ; The switch is lowered with a single icmp.

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