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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfree-zext.ll23 %load16 = and i32 %load, 65535
24 %load64 = zext i32 %load16 to i64
25 store i32 %load16, i32* %dst1, align 4
H A Daarch64-p2align-max-bytes-neoverse.ll52 %wide.load16 = load <4 x i32>, <4 x i32>* %7, align 4
56 %11 = add <4 x i32> %9, %wide.load16
H A Daarch64-p2align-max-bytes.ll55 %wide.load16 = load <4 x i32>, <4 x i32>* %7, align 4
59 %11 = add <4 x i32> %9, %wide.load16
/llvm-project-15.0.7/llvm/test/CodeGen/XCore/
H A Dload.ll21 define i32 @load16(i16* %p, i32 %offset) nounwind {
23 ; CHECK-LABEL: load16:
/llvm-project-15.0.7/libc/AOR_v20.02/networking/
H A Dchksum_common.h71 uint16_t load16(const void *ptr) in load16() function
95 sum += load16(cptr); in slurp_small()
H A Dchksum.c72 sum += load16(cptr); in __chksum()
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vhadd.ll438 %5 = sext <16 x i8> %wide.load16 to <16 x i16>
480 %5 = sext <8 x i16> %wide.load16 to <8 x i32>
522 %5 = sext <4 x i32> %wide.load16 to <4 x i64>
564 %5 = zext <16 x i8> %wide.load16 to <16 x i16>
606 %5 = zext <8 x i16> %wide.load16 to <8 x i32>
648 %5 = zext <4 x i32> %wide.load16 to <4 x i64>
690 %5 = zext <16 x i8> %wide.load16 to <16 x i16>
733 %5 = zext <8 x i16> %wide.load16 to <8 x i32>
776 %5 = zext <4 x i32> %wide.load16 to <4 x i64>
862 %5 = zext <8 x i16> %wide.load16 to <8 x i32>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dasan-check-memaccess-add.ll63 define void @load16(ptr nocapture readonly %x) nounwind {
64 ; CHECK-LABEL: load16:
H A Dmasked_load.ll501 ; SSE-NEXT: LBB5_13: ## %cond.load16
654 ; SSE2-NEXT: LBB6_13: ## %cond.load16
728 ; SSE42-NEXT: LBB6_13: ## %cond.load16
1169 ; SSE2-NEXT: LBB10_13: ## %cond.load16
1375 ; SSE2-NEXT: LBB11_13: ## %cond.load16
1835 ; SSE2-NEXT: LBB15_13: ## %cond.load16
2059 ; SSE2-NEXT: LBB16_13: ## %cond.load16
2497 ; SSE2-NEXT: LBB19_13: ## %cond.load16
2693 ; SSE2-NEXT: LBB20_13: ## %cond.load16
2881 ; SSE-NEXT: LBB21_13: ## %cond.load16
[all …]
H A Dmasked_gather.ll648 ; SSE-NEXT: # %bb.13: # %cond.load16
787 ; AVX1-NEXT: # %bb.13: # %cond.load16
917 ; AVX2-NEXT: # %bb.13: # %cond.load16
1032 ; AVX512-NEXT: # %bb.13: # %cond.load16
1212 ; SSE-NEXT: .LBB4_15: # %cond.load16
1480 ; AVX1-NEXT: .LBB4_13: # %cond.load16
1672 ; AVX2-NEXT: .LBB4_13: # %cond.load16
/llvm-project-15.0.7/llvm/test/Instrumentation/AddressSanitizer/
H A Dexperiment.ll43 define void @load16(i128* %p) sanitize_address {
47 ; CHECK-LABEL: define void @load16
H A Dexperiment-call.ll43 define void @load16(i128* %p) sanitize_address {
47 ; CHECK-LABEL: define void @load16
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Datomic-inline.cpp42 AM16 load16() { in load16() function
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dload.ll10 define i16 @load16(i16* %x) {
11 ; CHECK-LABEL: load16:
/llvm-project-15.0.7/llvm/test/CodeGen/ARC/
H A Dldst.ll13 ; CHECK-LABEL: load16
16 define i16 @load16(i16* %bp) nounwind {
/llvm-project-15.0.7/llvm/test/Instrumentation/DataFlowSanitizer/
H A Dload.ll38 define i16 @load16(i16* %p) {
39 ; CHECK-LABEL: @load16.dfsan
H A Dorigin_load.ll95 define i16 @load16(i1 %i, i16* %p) {
96 ; CHECK-LABEL: @load16.dfsan
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dnon-masked-load.mir33 %wide.load16 = load <16 x i8>, <16 x i8>* %lsr.iv2022
35 %13 = add <16 x i8> %12, %wide.load16
H A Dwrong-liveout-lsr-shift.mir34 …%wide.masked.load16 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv2022, i32 1, <8…
35 %13 = zext <8 x i8> %wide.masked.load16 to <8 x i16>
H A Dvctp16-reduce.mir34 …%wide.masked.load16 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv2022, i32 1, <8…
35 %13 = zext <8 x i8> %wide.masked.load16 to <8 x i16>
H A Dreductions.ll44 …%wide.masked.load16 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %i3, i32 1, <16 x …
45 %i4 = add <16 x i8> %wide.masked.load, %wide.masked.load16
183 …%wide.masked.load16 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %i3, i32 1, <16 x …
184 %i4 = sub <16 x i8> %wide.masked.load, %wide.masked.load16
/llvm-project-15.0.7/compiler-rt/lib/asan/tests/
H A Dasan_noinst_test.cpp317 CallAsanMemoryAccessAdd##reg##load16, \
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-masked-gather.ll706 ; RV64ZVE32F-NEXT: .LBB11_15: # %cond.load16
836 ; RV64ZVE32F-NEXT: .LBB12_15: # %cond.load16
1453 ; RV64ZVE32F-NEXT: .LBB22_15: # %cond.load16
1595 ; RV64ZVE32F-NEXT: .LBB23_15: # %cond.load16
1745 ; RV64ZVE32F-NEXT: .LBB24_15: # %cond.load16
1902 ; RV64ZVE32F-NEXT: .LBB25_15: # %cond.load16
2052 ; RV64ZVE32F-NEXT: .LBB26_15: # %cond.load16
4555 ; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
4836 ; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
5124 ; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dmem-op-cost-model.ll10 define <16 x i8> @load16(<16 x i8>* %ptr) {
11 ; CHECK: function 'load16'
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dmemory-dereferenceable.ll94 %load16 = load i8, i8 addrspace(1)* %dparam.align16, align 16

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