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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-ld3.s6 ld3 {v0.s, v1.s, v2.s}[0], [sp] label
8 ld3 {v0.2s, v1.2s, v2.2s}, [sp] label
10 ld3 {v0.d, v1.d, v2.d}[0], [sp] label
12 ld3 {v0.2d, v1.2d, v2.2d}, [sp] label
14 ld3 {v0.s, v1.s, v2.s}[0], [sp], #12 label
16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label
18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24 label
22 ld3 {v0.s, v1.s, v2.s}[0], [sp], x0 label
24 ld3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label
26 ld3 {v0.d, v1.d, v2.d}[0], [sp], x0 label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-ldN-reg+reg-addr-mode.ll90 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
91 ; CHECK-LABEL: ld3.nxv48i8:
101 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
102 ; CHECK-LABEL: ld3.nxv24i16:
112 ; CHECK-LABEL: ld3.nxv24f16:
122 ; CHECK-LABEL: ld3.nxv24bf16:
133 ; CHECK-LABEL: ld3.nxv12i32:
143 ; CHECK-LABEL: ld3.nxv12f32:
153 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) {
154 ; CHECK-LABEL: ld3.nxv6i64:
[all …]
H A Dsve-intrinsics-ldN-reg+imm-addr-mode.ll163 ; CHECK-LABEL: ld3.nxv48i8:
174 ; CHECK-LABEL: ld3.nxv48i8_lower_bound:
185 ; CHECK-LABEL: ld3.nxv48i8_upper_bound:
220 ; CHECK-LABEL: ld3.nxv48i8_outside_lower_bound:
245 ; CHECK-LABEL: ld3.nxv24i16:
256 ; CHECK-LABEL: ld3.nxv24f16:
267 ; CHECK-LABEL: ld3.nxv24bf16:
279 ; CHECK-LABEL: ld3.nxv12i32:
290 ; CHECK-LABEL: ld3.nxv12f32:
302 ; CHECK-LABEL: ld3.nxv6i64:
[all …]
H A Dsve-intrinsics-ldN-sret-reg+reg-addr-mode.ll90 define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8(<vscale x 16 x i…
91 ; CHECK-LABEL: ld3.nxv48i8:
101 define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld3.nxv24i16(<vscale x 8 x i…
102 ; CHECK-LABEL: ld3.nxv24i16:
112 ; CHECK-LABEL: ld3.nxv24f16:
122 ; CHECK-LABEL: ld3.nxv24bf16:
133 ; CHECK-LABEL: ld3.nxv12i32:
143 ; CHECK-LABEL: ld3.nxv12f32:
153 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld3.nxv6i64(<vscale x 2 x i1…
154 ; CHECK-LABEL: ld3.nxv6i64:
[all …]
H A Dsve-intrinsics-ldN-sret-reg+imm-addr-mode.ll173 ; CHECK-LABEL: ld3.nxv48i8:
185 ; CHECK-LABEL: ld3.nxv48i8_lower_bound:
197 ; CHECK-LABEL: ld3.nxv48i8_upper_bound:
233 ; CHECK-LABEL: ld3.nxv48i8_outside_lower_bound:
258 ; CHECK-LABEL: ld3.nxv24i16:
270 ; CHECK-LABEL: ld3.nxv24f16:
282 ; CHECK-LABEL: ld3.nxv24bf16:
295 ; CHECK-LABEL: ld3.nxv12i32:
307 ; CHECK-LABEL: ld3.nxv12f32:
320 ; CHECK-LABEL: ld3.nxv6i64:
[all …]
H A Daarch64-interleaved-ld-combine.ll34 %ld3 = load <4 x float>, <4 x float>* %gep3, align 16
38 %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
39 %sv4 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
96 %ld3 = load <4 x float>, <4 x float>* %gep3, align 16
100 %sv3 = shufflevector <4 x float> %ld3, <4 x float> %ld4, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
157 %ld3 = load <4 x float>, <4 x float>* %gep3, align 4
221 ; AS: ld3
235 %ld3 = load <4 x float>, <4 x float>* %gep3, align 16
270 ; AS-NOT: ld3
307 ; AS-NOT: ld3
[all …]
H A Darm64-neon-vector-list-spill.ll29 ; CHECK: ld3 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}]
33 …%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %arg1)
89 ; CHECK: ld3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}]
93 …%vld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(flo…
128 declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16*)
131 declare { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(float*)
H A Dsve-intrinsics-loads.ll407 …%res = call <vscale x 48 x i8> @llvm.aarch64.sve.ld3.nxv48i8.nxv16i1.p0i8(<vscale x 16 x i1> %pred…
420 …%res = call <vscale x 24 x i16> @llvm.aarch64.sve.ld3.nxv24i16.nxv8i1.p0i16(<vscale x 8 x i1> %pre…
473 …%res = call <vscale x 6 x i64> @llvm.aarch64.sve.ld3.nxv6i64.nxv2i1.p0i64(<vscale x 2 x i1> %pred,…
602 declare <vscale x 48 x i8> @llvm.aarch64.sve.ld3.nxv48i8.nxv16i1.p0i8(<vscale x 16 x i1>, i8*)
603 declare <vscale x 24 x i16> @llvm.aarch64.sve.ld3.nxv24i16.nxv8i1.p0i16(<vscale x 8 x i1>, i16*)
604 declare <vscale x 12 x i32> @llvm.aarch64.sve.ld3.nxv12i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
605 declare <vscale x 6 x i64> @llvm.aarch64.sve.ld3.nxv6i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
606 declare <vscale x 24 x half> @llvm.aarch64.sve.ld3.nxv24f16.nxv8i1.p0f16(<vscale x 8 x i1>, half*)
607 declare <vscale x 24 x bfloat> @llvm.aarch64.sve.ld3.nxv24bf16.nxv8i1.p0bf16(<vscale x 8 x i1>, bfl…
608 declare <vscale x 12 x float> @llvm.aarch64.sve.ld3.nxv12f32.nxv4i1.p0f32(<vscale x 4 x i1>, float*)
[all …]
H A Darm64-indexed-vector-ldst.ll1180 %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A)
1192 %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A)
1207 %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A)
1219 %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A)
1234 %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A)
1247 %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A)
1262 %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A)
1275 %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A)
1290 %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A)
1303 %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A)
[all …]
H A Darm64-ld1.ll20 ; CHECK: ld3.8b { v0, v1, v2 }, [x0]
55 ; CHECK: ld3.16b { v0, v1, v2 }, [x0]
90 ; CHECK: ld3.4h { v0, v1, v2 }, [x0]
125 ; CHECK: ld3.8h { v0, v1, v2 }, [x0]
160 ; CHECK: ld3.2s { v0, v1, v2 }, [x0]
195 ; CHECK: ld3.4s { v0, v1, v2 }, [x0]
230 ; CHECK: ld3.2d { v0, v1, v2 }, [x0]
335 ; CHECK: ld3.b { v0, v1, v2 }[1], [x0]
366 ; CHECK: ld3.h { v0, v1, v2 }[1], [x0]
397 ; CHECK: ld3.s { v0, v1, v2 }[1], [x0]
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-simd-ldst.s223 ld3.8b {v4, v5, v6}, [x19]
224 ld3.16b {v4, v5, v6}, [x19]
225 ld3.4h {v4, v5, v6}, [x19]
226 ld3.8h {v4, v5, v6}, [x19]
227 ld3.2s {v4, v5, v6}, [x19]
228 ld3.4s {v4, v5, v6}, [x19]
229 ld3.2d {v4, v5, v6}, [x19]
231 ld3.8b {v9, v10, v11}, [x9]
235 ld3.2s {v2, v3, v4}, [x19]
236 ld3.4s {v4, v5, v6}, [x29]
[all …]
H A Dneon-simd-ldst-multi-elem.s404 ld3 { v31.4s, v0.4s, v1.4s }, [sp]
405 ld3 { v0.2d, v1.2d, v2.2d }, [x0]
406 ld3 { v0.8b, v1.8b, v2.8b }, [x0]
408 ld3 { v31.2s, v0.2s, v1.2s }, [sp]
417 ld3 { v0.16b-v2.16b }, [x0]
418 ld3 { v15.8h-v17.8h }, [x15]
419 ld3 { v31.4s-v1.4s }, [sp]
420 ld3 { v0.2d-v2.2d }, [x0]
421 ld3 { v0.8b-v2.8b }, [x0]
422 ld3 { v15.4h-v17.4h }, [x15]
[all …]
H A Dneon-simd-ldst-one-elem.s105 ld3 { v0.b, v1.b, v2.b }[9], [x0]
106 ld3 { v15.h, v16.h, v17.h }[7], [x15]
107 ld3 { v31.s, v0.s, v1.s }[3], [sp]
108 ld3 { v0.d, v1.d, v2.d }[1], [x0]
266 ld3 { v0.b, v1.b, v2.b }[9], [x0], #3
267 ld3 { v15.h, v16.h, v17.h }[7], [x15], #6
268 ld3 { v31.s, v0.s, v1.s }[3], [sp], x3
269 ld3 { v0.d, v1.d, v2.d }[1], [x0], x6
H A Dneon-simd-post-ldst-multi-elem.s150 ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1
151 ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
152 ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48
153 ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48
154 ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2
155 ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
156 ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/SystemZ/
H A Dmem-interleaving-costs-02.ll17 ; CHECK: LV: Found an estimated cost of 0 for VF 4 For instruction: %ld3 = load i16
33 %ld3 = load i16, i16* %ptr3
36 %a3 = add i16 %a2, %ld3
81 ; CHECK: LV: Found an estimated cost of 0 for VF 2 For instruction: %ld3 = load i8
97 %ld3 = load i8, i8* %ptr3
100 %a3 = add i8 %a2, %ld3
121 ; CHECK: LV: Found an estimated cost of 0 for VF 2 For instruction: %ld3 = load i8
137 %ld3 = load i8, i8* %ptr3
140 %a3 = add i8 %a2, %ld3
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpromote-alloca-array-allocation.ll22 %ld3 = load i32, i32* %arrayidx12
24 store i32 %ld3, i32 addrspace(1)* %arrayidx13
44 %ld3 = load i32, i32* %arrayidx12
46 store i32 %ld3, i32 addrspace(1)* %arrayidx13
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dtsc-s116.ll49 %ld3 = load float, float* %gep3
53 %mul2 = fmul fast float %ld3, %ld2
54 %mul3 = fmul fast float %ld4, %ld3
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dbswap.ll69 %ld3 = load i64, i64* getelementptr inbounds ([4 x i64], [4 x i64]* @src64, i64 0, i64 3), align 4
73 %bswap3 = call i64 @llvm.bswap.i64(i64 %ld3)
91 %ld3 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @src32, i32 0, i64 3), align 4
95 %bswap3 = call i32 @llvm.bswap.i32(i32 %ld3)
122 %ld3 = load i32, i32* getelementptr inbounds ([8 x i32], [8 x i32]* @src32, i32 0, i64 3), align 2
130 %bswap3 = call i32 @llvm.bswap.i32(i32 %ld3)
156 …%ld3 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 3), align…
164 %bswap3 = call i16 @llvm.bswap.i16(i16 %ld3)
199 …%ld3 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @src16, i16 0, i64 3), ali…
215 %bswap3 = call i16 @llvm.bswap.i16(i16 %ld3)
H A Duitofp.ll62 %cvt3 = uitofp i64 %ld3 to double
112 %cvt3 = uitofp i64 %ld3 to double
194 %cvt3 = uitofp i32 %ld3 to double
244 %cvt3 = uitofp i32 %ld3 to double
404 %cvt3 = uitofp i8 %ld3 to double
454 %cvt3 = uitofp i8 %ld3 to double
537 %cvt3 = uitofp i64 %ld3 to float
572 %cvt3 = uitofp i64 %ld3 to float
602 %cvt3 = uitofp i32 %ld3 to float
896 %cvt3 = uitofp i8 %ld3 to float
[all …]
H A Dsitofp.ll113 %cvt3 = sitofp i64 %ld3 to double
202 %cvt3 = sitofp i64 %ld3 to double
257 %cvt3 = sitofp i32 %ld3 to double
307 %cvt3 = sitofp i32 %ld3 to double
467 %cvt3 = sitofp i8 %ld3 to double
517 %cvt3 = sitofp i8 %ld3 to double
591 %cvt3 = sitofp i64 %ld3 to float
626 %cvt3 = sitofp i64 %ld3 to float
656 %cvt3 = sitofp i32 %ld3 to float
950 %cvt3 = sitofp i8 %ld3 to float
[all …]
H A Dsitofp-inseltpoison.ll113 %cvt3 = sitofp i64 %ld3 to double
202 %cvt3 = sitofp i64 %ld3 to double
257 %cvt3 = sitofp i32 %ld3 to double
307 %cvt3 = sitofp i32 %ld3 to double
467 %cvt3 = sitofp i8 %ld3 to double
517 %cvt3 = sitofp i8 %ld3 to double
591 %cvt3 = sitofp i64 %ld3 to float
626 %cvt3 = sitofp i64 %ld3 to float
656 %cvt3 = sitofp i32 %ld3 to float
950 %cvt3 = sitofp i8 %ld3 to float
[all …]
/llvm-project-15.0.7/clang/test/Sema/
H A Dwarn-literal-range.c33 long double ld3 = 0x0.42p42L; // no-warning variable
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/AMDGPU/
H A Dunroll-analyze-small-loops.ll49 %ld3 = load float, float addrspace(5)* %arrayidx3, align 4
51 %add4 = fadd contract float %ld3, %mul4
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/AArch64/
H A Dintrinsics.ll140 ; Check that @llvm.aarch64.neon.ld3 is not optimized away by Early CSE due
141 ; to mismatch between st2 and ld3.
143 ; CHECK: call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0
160 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %a)
195 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %a)
216 declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr)
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dintrinsic-arg-overloading-struct-ret.ll32 ; CHECK-NEXT: llvm.aarch64.neon.ld3.v4i32
34 %res = call { <4 x i32>, <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32(<4 x i32>* %ptr)
37 declare { <4 x i32>, <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32(<4 x i32>* %ptr)

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