| /llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/ |
| H A D | ld2h-diagnostics.s | 7 ld2h {z12.h, z13.h}, p4/z, [x12, #-18, MUL VL] label 12 ld2h {z7.h, z8.h}, p3/z, [x1, #16, MUL VL] label 26 ld2h {z7.h, z8.h}, p3/z, [x1, #5, MUL VL] label 35 ld2h { z0.h, z1.h }, p0/z, [x0, x0] label 40 ld2h { z0.h, z1.h }, p0/z, [x0, xzr] label 50 ld2h { z0.h, z1.h }, p0/z, [x0, w0] label 73 ld2h { }, p0/z, [x0] label 78 ld2h { z0.h, z1.h, z2.h }, p0/z, [x0] label 83 ld2h { z0.h, z1.s }, p0/z, [x0] label 88 ld2h { z0.h, z2.h }, p0/z, [x0] label [all …]
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| H A D | ld2h.s | 12 ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1] label 18 ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1] label 24 ld2h { z0.h, z1.h }, p0/z, [x0] label 30 ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl] label 36 ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] label
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | float16-declarations.cpp | 141 _Float16 ld2h = 42.0l; in main() local
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| /llvm-project-15.0.7/clang/test/AST/ |
| H A D | float16.cpp | 337 _Float16 ld2h = 42.0l; in main() local
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | sve-ldN.mir | 56 ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [sp, #-16, mul vl] 57 ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [sp, #14, mul vl] 186 ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [x8, #-16, mul vl] 188 ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [x8, #14, mul vl]
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| H A D | sve-intrinsics-ldN-reg+reg-addr-mode.ll | 16 ; ld2h 20 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1] 30 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1] 40 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1]
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| H A D | sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll | 16 ; ld2h 20 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1] 30 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1] 40 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1]
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| H A D | sve-intrinsics-ldN-reg+imm-addr-mode.ll | 81 ; ld2h 85 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, #14, mul vl] 96 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, #-16, mul vl] 107 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, #12, mul vl]
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| H A D | sve-intrinsics-loads.ll | 330 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0] 339 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0] 348 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0]
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| H A D | sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll | 84 ; ld2h 89 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x8] 101 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x8] 113 ; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x8]
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| /llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Neoverse/ |
| H A D | N2-sve-instructions.s | 1706 ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1] label 1707 ld2h { z0.h, z1.h }, p0/z, [x0] label 1708 ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] label 1709 ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl] label 1710 ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1] label 5633 # CHECK-NEXT: 2 9 0.50 * U ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1] 5634 # CHECK-NEXT: 2 8 0.50 * U ld2h { z0.h, z1.h }, p0/z, [x0] 5635 # CHECK-NEXT: 2 8 0.50 * U ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul… 5636 # CHECK-NEXT: 2 8 0.50 * U ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mu… 5637 # CHECK-NEXT: 2 9 0.50 * U ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #… [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA64FX.td | 3035 // [246] "ld2h $Zt, $Pg/z, [$Rn, $Rm]"; 3038 // [247] "ld2h $Zt, $Pg/z, [$Rn, $imm4, mul vl]";
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| H A D | AArch64SVEInstrInfo.td | 974 defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h, "ld2h", simm4s2>; 988 def LD2H : sve_mem_eld_ss<0b01, 0b01, ZZ_h, "ld2h", GPR64NoXZRshifted16>;
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