Home
last modified time | relevance | path

Searched refs:ld1 (Results 1 – 25 of 113) sorted by relevance

12345

/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-ld1.s6 ld1 {v0.s}[0], [sp] label
8 ld1 {v0.2s}, [sp] label
9 ld1 {v0.2s, v1.2s}, [sp] label
13 ld1 {v0.d}[0], [sp] label
15 ld1 {v0.2d}, [sp] label
20 ld1 {v0.s}[0], [sp], #4 label
22 ld1 {v0.2s}, [sp], #8 label
27 ld1 {v0.d}[0], [sp], #8 label
29 ld1 {v0.2d}, [sp], #16 label
36 ld1 {v0.2s}, [sp], x0 label
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s238 ld1 { v0.16b }, [x0]
239 ld1 { v15.8h }, [x15]
240 ld1 { v31.4s }, [sp]
241 ld1 { v0.2d }, [x0]
242 ld1 { v0.8b }, [x0]
243 ld1 { v15.4h }, [x15]
244 ld1 { v31.2s }, [sp]
245 ld1 { v0.1d }, [x0]
278 ld1 { v0.2d-v1.2d }, [x0]
279 ld1 { v0.8b-v1.8b }, [x0]
[all …]
H A Dneon-simd-post-ldst-multi-elem.s8 ld1 { v0.16b }, [x0], x1
9 ld1 { v15.8h }, [x15], x2
10 ld1 { v31.4s }, [sp], #16
11 ld1 { v0.2d }, [x0], #16
12 ld1 { v0.8b }, [x0], x2
13 ld1 { v15.4h }, [x15], x3
14 ld1 { v31.2s }, [sp], #8
15 ld1 { v0.1d }, [x0], #8
40 ld1 { v0.2d, v1.2d }, [x0], #32
41 ld1 { v0.8b, v1.8b }, [x0], x2
[all …]
H A Darm64-simd-ldst.s4 ld1.8b {v0}, [x1]
5 ld1.8b {v0, v1}, [x1]
9 ld1.8b {v3}, [x1]
10 ld1.8b {v3, v4}, [x2]
14 ld1.16b {v0}, [x1]
19 ld1.4h {v0}, [x1]
24 ld1.8h {v0}, [x1]
29 ld1.2s {v0}, [x1]
34 ld1.4s {v0}, [x1]
39 ld1.1d {v0}, [x1]
[all …]
H A Dneon-simd-ldst-one-elem.s83 ld1 { v0.b }[9], [x0]
84 ld1 { v15.h }[7], [x15]
85 ld1 { v31.s }[3], [sp]
86 ld1 { v0.d }[1], [x0]
244 ld1 { v0.b }[9], [x0], #1
245 ld1 { v15.h }[7], [x15], x9
246 ld1 { v31.s }[3], [sp], x6
247 ld1 { v0.d }[1], [x0], #8
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-ld1.ll215 declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, i8*)
217 declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1>, i8*)
218 declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1>, i16*)
219 declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1>, half*)
222 declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1>, i8*)
223 declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1>, i16*)
224 declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1>, i32*)
227 declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1>, i8*)
228 declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1>, i16*)
229 declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1>, i32*)
[all …]
H A Dsve-coalesce-ptrue-intrinsics.ll9 declare <vscale x 16 x i32> @llvm.aarch64.sve.ld1.nxv16i32(<vscale x 16 x i1>, i32*)
10 declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1>, i32*)
11 declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1>, i32*)
12 declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1>, i16*)
13 declare <vscale x 8 x i32> @llvm.aarch64.sve.ld1.nxv8i32(<vscale x 8 x i1>, i32*)
30 %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %1, i32* %addr)
32 %4 = call <vscale x 8 x i32> @llvm.aarch64.sve.ld1.nxv8i32(<vscale x 8 x i1> %3, i32* %addr)
48 %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %1, i32* %addr)
50 %4 = call <vscale x 8 x i32> @llvm.aarch64.sve.ld1.nxv8i32(<vscale x 8 x i1> %3, i32* %addr)
75 %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %1, i32* %addr)
[all …]
H A Darm64-vcvt.ll9 ;CHECK-NOT: ld1
19 ;CHECK-NOT: ld1
29 ;CHECK-NOT: ld1
38 ;CHECK-NOT: ld1
52 ;CHECK-NOT: ld1
61 ;CHECK-NOT: ld1
70 ;CHECK-NOT: ld1
79 ;CHECK-NOT: ld1
93 ;CHECK-NOT: ld1
102 ;CHECK-NOT: ld1
[all …]
H A Dsve-intrinsics-ld1-addressing-mode-reg-reg.ll230 declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, i8*)
232 declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1>, i8*)
233 declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1>, i16*)
234 declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1>, half*)
237 declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1>, i8*)
238 declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1>, i16*)
239 declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1>, i32*)
242 declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1>, i8*)
243 declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1>, i16*)
244 declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1>, i32*)
[all …]
H A Darm64-vmovn.ll5 ;CHECK-NOT: ld1
14 ;CHECK-NOT: ld1
23 ;CHECK-NOT: ld1
32 ;CHECK-NOT: ld1
42 ;CHECK-NOT: ld1
52 ;CHECK-NOT: ld1
62 ;CHECK-NOT: ld1
71 ;CHECK-NOT: ld1
80 ;CHECK-NOT: ld1
89 ;CHECK-NOT: ld1
[all …]
H A Dsve-intrinsics-gather-loads-32bit-scaled-offsets.ll16 …%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16(<vscale x 4 x i1> …
28 …%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16(<vscale x 4 x i1> …
40 …%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv2i16(<vscale x 2 x i1> …
52 …%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv2i16(<vscale x 2 x i1> …
65 …%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i32(<vscale x 4 x i1> …
76 …%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32(<vscale x 4 x i1> …
87 …%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv2i32(<vscale x 2 x i1> …
99 …%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv2i32(<vscale x 2 x i1> …
134 …%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv2i64(<vscale x 2 x i1> …
145 …%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv2i64(<vscale x 2 x i1> …
[all …]
H A Dsve-intrinsics-gather-loads-32bit-unscaled-offsets.ll16 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1> %pg,
28 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1> %pg,
40 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i8(<vscale x 2 x i1> %pg,
52 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1> %pg,
65 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16(<vscale x 4 x i1> %pg,
77 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1> %pg,
89 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i16(<vscale x 2 x i1> %pg,
101 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1> %pg,
114 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32(<vscale x 4 x i1> %pg,
234 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1> %pg,
[all …]
H A Dsve-intrinsics-gather-loads-vector-base-scalar-offset.ll15 …%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x…
27 …%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x…
40 …%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale…
52 …%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale…
65 …%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale…
76 …%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale…
100 …%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64(<vscale…
127 …%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x…
139 …%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x…
152 …%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale…
[all …]
H A Dsve-intrinsics-ld1-addressing-mode-reg-imm.ll322 declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, i8*)
324 declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1>, i8*)
325 declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1>, i16*)
326 declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1>, half*)
329 declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1>, i8*)
330 declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1>, i16*)
331 declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1>, i32*)
334 declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1>, i8*)
335 declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1>, i16*)
336 declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1>, i32*)
[all …]
H A Darm64-big-endian-bitconverts.ll30 ; CHECK: ld1 { v{{[0-9]+}}.2s }
43 ; CHECK: ld1 { v{{[0-9]+}}.2s }
56 ; CHECK: ld1 { v{{[0-9]+}}.4h }
71 ; CHECK: ld1 { v{{[0-9]+}}.4h }
84 ; CHECK: ld1 { v{{[0-9]+}}.8b }
121 ; CHECK: ld1 { v{{[0-9]+}}.2s }
134 ; CHECK: ld1 { v{{[0-9]+}}.2s }
147 ; CHECK: ld1 { v{{[0-9]+}}.4h }
160 ; CHECK: ld1 { v{{[0-9]+}}.4h }
176 ; CHECK: ld1 { v{{[0-9]+}}.8b }
[all …]
H A Dsve-intrinsics-gather-loads-vector-base-imm-offset.ll15 …%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x…
27 …%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x…
40 …%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale…
52 …%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale…
65 …%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale…
76 …%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale…
100 …%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64(<vscale…
128 …%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x…
140 …%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x…
197 …%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x…
[all …]
H A Daarch64-interleaved-ld-combine.ll32 %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
94 %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
155 %ld1 = load <4 x float>, <4 x float>* %gep1, align 4
197 %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
233 %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
259 ; CHECK-NEXT: %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
281 %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
314 %ld1 = load volatile <4 x float>, <4 x float>* %gep1, align 16
330 ; CHECK-NEXT: store <4 x float> %ld1, <4 x float>* %gep2, align 16
347 %ld1 = load <4 x float>, <4 x float>* %gep1, align 16
[all …]
H A Dsve-intrinsics-gather-loads-64bit-unscaled-offset.ll14 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,
26 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,
38 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,
50 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.nxv2i64(<vscale x 2 x i1> %pg,
77 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,
89 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,
101 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,
121 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,
136 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,
199 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,
[all …]
H A Darm64-trn.ll17 ; CHECKBE-NEXT: ld1 { v0.8b }, [x0]
18 ; CHECKBE-NEXT: ld1 { v1.8b }, [x1]
44 ; CHECKBE-NEXT: ld1 { v0.4h }, [x0]
45 ; CHECKBE-NEXT: ld1 { v1.4h }, [x1]
69 ; CHECKBE-NEXT: ld1 { v0.4h }, [x0]
70 ; CHECKBE-NEXT: ld1 { v1.4h }, [x1]
95 ; CHECKBE-NEXT: ld1 { v0.2s }, [x0]
96 ; CHECKBE-NEXT: ld1 { v1.2s }, [x1]
122 ; CHECKBE-NEXT: ld1 { v0.2s }, [x0]
123 ; CHECKBE-NEXT: ld1 { v1.2s }, [x1]
[all …]
H A Dsve-intrinsics-gather-loads-64bit-scaled-offset.ll14 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.index.nxv2i16(<vscale x 2 x i1> %pg,
26 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.index.nxv2i32(<vscale x 2 x i1> %pg,
38 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.index.nxv2i64(<vscale x 2 x i1> %pg,
49 …%load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.index.nxv2f64(<vscale x 2 x i1> %p…
65 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.index.nxv2i16(<vscale x 2 x i1> %pg,
77 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.index.nxv2i32(<vscale x 2 x i1> %pg,
97 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.index.nxv2i16(<vscale x 2 x i1> %pg,
112 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.index.nxv2i32(<vscale x 2 x i1> %pg,
127 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.index.nxv2i64(<vscale x 2 x i1> %pg,
160 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.index.nxv2i16(<vscale x 2 x i1> %pg,
[all …]
H A Dneon-extadd.ll450 ; CHECK-NEXT: ld1 { v0.b }[1], [x9]
452 ; CHECK-NEXT: ld1 { v2.b }[1], [x10]
458 ; CHECK-NEXT: ld1 { v0.b }[2], [x9]
460 ; CHECK-NEXT: ld1 { v3.b }[1], [x10]
465 ; CHECK-NEXT: ld1 { v0.b }[3], [x9]
469 ; CHECK-NEXT: ld1 { v2.b }[2], [x9]
478 ; CHECK-NEXT: ld1 { v0.b }[5], [x9]
492 ; CHECK-NEXT: ld1 { v0.b }[7], [x9]
498 ; CHECK-NEXT: ld1 { v2.b }[6], [x9]
503 ; CHECK-NEXT: ld1 { v3.b }[6], [x9]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dselect-ext.ll13 %ld1 = load volatile i8, ptr %p
16 %cond.v = select i1 %c, i8 %ld2, i8 %ld1
29 %ld1 = load volatile i8, ptr %p
30 %ext_ld1 = zext i8 %ld1 to i16
49 %ld1 = load volatile i8, ptr %p
50 %ext_ld1 = sext i8 %ld1 to i16
66 %ld1 = load volatile i8, ptr %p
86 %ld1 = load volatile <2 x i32>, ptr %p
103 %ld1 = load volatile <2 x i32>, ptr %p
123 %ld1 = load volatile <2 x i32>, ptr %p
[all …]
H A Datom-cmpb.ll15 %ld1 = load i8, ptr %rd_p, align 1
18 %x4 = xor i8 %ld1, -1
20 %cmp34 = icmp ult i8 %ld2, %ld1
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/SystemZ/
H A Dmem-interleaving-costs-02.ll15 ; CHECK: LV: Found an estimated cost of 0 for VF 4 For instruction: %ld1 = load i16
29 %ld1 = load i16, i16* %ptr1
34 %a1 = add i16 %ld0, %ld1
79 ; CHECK: LV: Found an estimated cost of 0 for VF 2 For instruction: %ld1 = load i8
93 %ld1 = load i8, i8* %ptr1
98 %a1 = add i8 %ld0, %ld1
119 ; CHECK: LV: Found an estimated cost of 0 for VF 2 For instruction: %ld1 = load i8
133 %ld1 = load i8, i8* %ptr1
138 %a1 = add i8 %ld0, %ld1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpromote-alloca-array-allocation.ll15 %ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
16 %arrayidx3 = getelementptr inbounds i32, i32* %stack, i32 %ld1
37 %ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
38 %arrayidx3 = getelementptr inbounds i32, i32* %stack, i32 %ld1

12345