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Searched refs:isVerilogBegin (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/clang/lib/Format/
H A DFormatToken.h1709 bool isVerilogBegin(const FormatToken &Tok) const { in isVerilogBegin() function
1730 (Style.isVerilog() ? isVerilogBegin(Tok) : Tok.is(tok::l_brace)); in isBlockBegin()
H A DUnwrappedLineParser.cpp843 (Style.isVerilog() && Keywords.isVerilogBegin(*FormatTok))) && in parseBlock()