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Searched refs:isPureSlot0 (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp1114 if (MI.mayStore() && HII.isRestrictNoSlot1Store(MJ) && HII.isPureSlot0(MJ)) in cannotCoexistAsymm()
1538 if (LoadJ && LoadI && HII->isPureSlot0(J)) { in isLegalToPacketizeTogether()
1855 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); in shouldAddToPacket()
H A DHexagonInstrInfo.h395 bool isPureSlot0(const MachineInstr &MI) const;
H A DHexagonInstrInfo.cpp4396 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const { in isPureSlot0() function in HexagonInstrInfo