Home
last modified time | relevance | path

Searched refs:isPre (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp135 bool isPre = (AM == ISD::PRE_DEC); in selectIndexedLoad() local
140 if ((!isPre && Offs != 1) || (isPre && Offs != -1)) { in selectIndexedLoad()
144 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi; in selectIndexedLoad()
148 if ((!isPre && Offs != 2) || (isPre && Offs != -2)) { in selectIndexedLoad()
152 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi; in selectIndexedLoad()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1593 if (LoadedVT == MVT::i32 && isPre && in tryARMIndexedLoad()
1597 } else if (LoadedVT == MVT::i32 && !isPre && in tryARMIndexedLoad()
1603 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1610 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1611 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1619 if (isPre && in tryARMIndexedLoad()
1623 } else if (!isPre && in tryARMIndexedLoad()
1703 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; in tryT2IndexedLoad()
1742 bool isSExtLd, isPre; in tryMVEIndexedLoad() local
1761 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
[all …]
H A DARMInstrFormats.td782 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
789 let Inst{24} = isPre; // P bit
791 let Inst{21} = isPre; // W bit
795 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
798 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
813 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
816 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
832 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
871 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
878 let Inst{24} = isPre; // P bit
[all …]
H A DARMBaseInstrInfo.cpp186 bool isPre = false; in convertToThreeAddress() local
190 isPre = true; in convertToThreeAddress()
275 if (isPre) { in convertToThreeAddress()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGExprScalar.cpp609 bool isInc, bool isPre);
2513 bool isInc, bool isPre) { in EmitScalarPrePostIncDec() argument
2527 if (isPre) { in EmitScalarPrePostIncDec()
2555 return isPre ? Builder.CreateBinOp(op, old, amt) : old; in EmitScalarPrePostIncDec()
2806 return isPre ? value : input; in EmitScalarPrePostIncDec()
2817 return isPre ? value : input; in EmitScalarPrePostIncDec()
4902 bool isInc, bool isPre) { in EmitScalarPrePostIncDec() argument
4903 return ScalarExprEmitter(*this).EmitScalarPrePostIncDec(E, LV, isInc, isPre); in EmitScalarPrePostIncDec()
H A DCGExprComplex.cpp192 bool isInc, bool isPre) { in VisitPrePostIncDec() argument
194 return CGF.EmitComplexPrePostIncDec(E, LV, isInc, isPre); in VisitPrePostIncDec()
H A DCodeGenFunction.h3011 bool isInc, bool isPre);
3013 bool isInc, bool isPre);
H A DCGExpr.cpp1032 bool isInc, bool isPre) { in EmitComplexPrePostIncDec() argument
1063 return isPre ? IncVal : InVal; in EmitComplexPrePostIncDec()