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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dlegalize-invert-br_cc.ll6 …ze::ExpandNode(llvm::SDNode*): Assertion `!NeedInvert && "Don't know how to invert BR_CC!"' failed.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsink-not-into-another-hand-of-and.ll8 ; iff y is free to invert and all uses of z can be freely updated.
76 ; FIXME: we could invert all uses of %i1 here
H A Dsink-not-into-another-hand-of-or.ll8 ; iff y is free to invert and all uses of z can be freely updated.
76 ; FIXME: we could invert all uses of %i1 here
H A Dcanonicalize-selects-icmp-condition-bittest.ll33 ; Can't invert all users of original condition
H A Dxor-of-icmps-with-extra-uses.ll89 ; Can invert 'not'.
H A Dcanonicalize-clamp-like-pattern-between-zero-and-positive-threshold.ll16 ; Also, ULT predicate can also be UGE; or UGT iff C0 != -1 (+invert result)
17 ; Also, SLT predicate can also be SGE; or SGT iff C2 != INT_MAX (+invert res.)
H A Dcanonicalize-clamp-like-pattern-between-negative-and-positive-thresholds.ll16 ; Also, ULT predicate can also be UGE; or UGT iff C0 != -1 (+invert result)
17 ; Also, SLT predicate can also be SGE; or SGT iff C2 != INT_MAX (+invert res.)
H A Dinvert-variable-mask-in-masked-merge-scalar.ll6 ; We can de-invert the M:
H A Dicmp-sub.ll538 ; TODO: It might be ok to replace the "SUB == 0" in this example if codegen can invert it.
H A Dinvert-variable-mask-in-masked-merge-vector.ll6 ; We can de-invert the M:
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dbranch-relax-asm.ll6 ; of the limited range we gave tbz. So branch relaxation has to invert the
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DScaledNumber.h527 return get(N).invert(); in getInverse()
676 ScaledNumber &invert() { return *this = ScaledNumber::get(1) / *this; } in invert() function
677 ScaledNumber inverse() const { return ScaledNumber(*this).invert(); } in inverse()
/llvm-project-15.0.7/clang-tools-extra/clangd/test/
H A Dprotocol.test6 # Note that we invert the test because we intent to let clangd exit prematurely.
/llvm-project-15.0.7/lld/ELF/
H A DScriptParser.cpp1740 bool invert = false; in readMemoryAttributes() local
1744 invert = !invert; in readMemoryAttributes()
1761 if (invert) { in readMemoryAttributes()
/llvm-project-15.0.7/llvm/lib/Support/
H A Dregcomp.c800 int invert = 0; in p_bracket() local
822 invert++; /* make note to invert set at end */ in p_bracket()
851 if (invert) { in p_bracket()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dbt.ll1042 define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind {
1043 ; X86-LABEL: invert:
1051 ; X64-LABEL: invert:
H A Dvector-compare-simplify.ll339 ; the constant pool load, but the alternative is a cmpeq+invert which is 3 instructions.
H A Dtest-vs-bittest.ll78 ; initial IR. One has an extra invert of the setcc. This previous caused one
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlower-neon-vector-fcmp.mir340 ; Needs two compares. No invert.
365 ; Needs two compares. No invert.
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGMIR.rst116 GPR then we can equivalently G_XOR the sign bit with 1 to invert it.
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dcompare.ll714 %invert = xor i1 %cond, 1
715 %s = select i1 %invert, i32 0, i32 1
1142 %invert = xor <2 x i1> %cond, <i1 1, i1 1>
1143 %s = select <2 x i1> %invert, <2 x i32> <i32 0, i32 0>, <2 x i32> <i32 1, i32 1>
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td2010 Similarly to the byte pattern, we invert the bits of the index, but we
2011 AND with 0x4 (i.e. clear all bits of the index and invert bit 61).
2110 - The order of elements after the move to GPR is reversed, so we invert
2128 - The order of elements after the move to GPR is reversed, so we invert
2146 - The order of elements after the move to GPR is reversed, so we invert
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DREADME.txt79 when it can invert the result of the compare for free.
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp649 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); in createCMovFP() local
652 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, in createCMovFP()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td1034 // the always true/false semantics we would invert if we just decremented the

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