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/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dfullfp16-neon-neg.txt6 # CHECK: warning: invalid instruction encoding
8 # CHECK: warning: invalid instruction encoding
10 # CHECK: warning: invalid instruction encoding
12 # CHECK: warning: invalid instruction encoding
14 # CHECK: warning: invalid instruction encoding
16 # CHECK: warning: invalid instruction encoding
18 # CHECK: warning: invalid instruction encoding
20 # CHECK: warning: invalid instruction encoding
22 # CHECK: warning: invalid instruction encoding
24 # CHECK: warning: invalid instruction encoding
[all …]
H A Dfullfp16-neg.txt5 # CHECK: warning: invalid instruction encoding
7 # CHECK: warning: invalid instruction encoding
9 # CHECK: warning: invalid instruction encoding
11 # CHECK: warning: invalid instruction encoding
13 # CHECK: warning: invalid instruction encoding
15 # CHECK: warning: invalid instruction encoding
17 # CHECK: warning: invalid instruction encoding
19 # CHECK: warning: invalid instruction encoding
21 # CHECK: warning: invalid instruction encoding
23 # CHECK: warning: invalid instruction encoding
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dfullfp16-neon-arm-neg.txt3 # CHECK: warning: invalid instruction encoding
4 # CHECK: warning: invalid instruction encoding
8 # CHECK: warning: invalid instruction encoding
9 # CHECK: warning: invalid instruction encoding
13 # CHECK: warning: invalid instruction encoding
14 # CHECK: warning: invalid instruction encoding
18 # CHECK: warning: invalid instruction encoding
19 # CHECK: warning: invalid instruction encoding
23 # CHECK: warning: invalid instruction encoding
24 # CHECK: warning: invalid instruction encoding
[all …]
H A Dfullfp16-neon-thumb-neg.txt3 # CHECK: warning: invalid instruction encoding
4 # CHECK: warning: invalid instruction encoding
8 # CHECK: warning: invalid instruction encoding
9 # CHECK: warning: invalid instruction encoding
13 # CHECK: warning: invalid instruction encoding
14 # CHECK: warning: invalid instruction encoding
18 # CHECK: warning: invalid instruction encoding
19 # CHECK: warning: invalid instruction encoding
23 # CHECK: warning: invalid instruction encoding
24 # CHECK: warning: invalid instruction encoding
[all …]
H A Dfullfp16-arm-neg.txt3 # CHECK: warning: invalid instruction encoding
6 # CHECK: warning: invalid instruction encoding
9 # CHECK: warning: invalid instruction encoding
12 # CHECK: warning: invalid instruction encoding
15 # CHECK: warning: invalid instruction encoding
18 # CHECK: warning: invalid instruction encoding
21 # CHECK: warning: invalid instruction encoding
24 # CHECK: warning: invalid instruction encoding
27 # CHECK: warning: invalid instruction encoding
30 # CHECK: warning: invalid instruction encoding
[all …]
H A Dfullfp16-thumb-neg.txt3 # CHECK: warning: invalid instruction encoding
6 # CHECK: warning: invalid instruction encoding
9 # CHECK: warning: invalid instruction encoding
12 # CHECK: warning: invalid instruction encoding
15 # CHECK: warning: invalid instruction encoding
18 # CHECK: warning: invalid instruction encoding
21 # CHECK: warning: invalid instruction encoding
24 # CHECK: warning: invalid instruction encoding
27 # CHECK: warning: invalid instruction encoding
30 # CHECK: warning: invalid instruction encoding
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddirective-arch_extension-fp.s20 @ CHECK-V7: instruction requires: FPARMv8
23 @ CHECK-V7: instruction requires: FPARMv8
25 @ CHECK-V7: instruction requires: FPARMv8
27 @ CHECK-V7: instruction requires: FPARMv8
29 @ CHECK-V7: instruction requires: FPARMv8
31 @ CHECK-V7: instruction requires: FPARMv8
33 @ CHECK-V7: instruction requires: FPARMv8
36 @ CHECK-V7: instruction requires: FPARMv8
38 @ CHECK-V7: instruction requires: FPARMv8
156 @ CHECK: instruction requires: FPARMv8
[all …]
H A Dfullfp16-neg.s5 @ CHECK: instruction requires: full half-float
8 @ CHECK: instruction requires: full half-float
11 @ CHECK: instruction requires: full half-float
14 @ CHECK: instruction requires: full half-float
17 @ CHECK: instruction requires: full half-float
20 @ CHECK: instruction requires: full half-float
23 @ CHECK: instruction requires: full half-float
26 @ CHECK: instruction requires: full half-float
29 @ CHECK: instruction requires: full half-float
32 @ CHECK: instruction requires: full half-float
[all …]
H A Dfullfp16-neon-neg.s8 @ CHECK: instruction requires: {{full half-float|NEON}}
9 @ CHECK: instruction requires: {{full half-float|NEON}}
13 @ CHECK: instruction requires: {{full half-float|NEON}}
14 @ CHECK: instruction requires: {{full half-float|NEON}}
18 @ CHECK: instruction requires: {{full half-float|NEON}}
19 @ CHECK: instruction requires: {{full half-float|NEON}}
23 @ CHECK: instruction requires: {{full half-float|NEON}}
24 @ CHECK: instruction requires: {{full half-float|NEON}}
28 @ CHECK: instruction requires: {{full half-float|NEON}}
29 @ CHECK: instruction requires: {{full half-float|NEON}}
[all …]
H A Ddirective-arch_extension-simd.s20 @ CHECK-V7: error: instruction requires: FPARMv8
22 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
30 @ CHECK-V7: error: instruction requires: FPARMv8
32 @ CHECK-V7: error: instruction requires: FPARMv8
34 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
128 @ CHECK: error: instruction requires: FPARMv8
130 @ CHECK: error: instruction requires: FPARMv8
[all …]
H A Dmve-load-store.s8 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
12 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
16 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
20 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
24 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
28 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
32 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
36 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
40 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
44 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
[all …]
H A Ddirective-arch_extension-crypto.s62 @ CHECK-V8: error: instruction requires: aes
66 @ CHECK-V8: error: instruction requires: aes
69 @ CHECK-V8: error: instruction requires: aes
72 @ CHECK-V8: error: instruction requires: aes
75 @ CHECK-V8: error: instruction requires: aes
79 @ CHECK-V8: error: instruction requires: sha2
82 @ CHECK-V8: error: instruction requires: sha2
85 @ CHECK-V8: error: instruction requires: sha2
89 @ CHECK-V8: error: instruction requires: sha2
92 @ CHECK-V8: error: instruction requires: sha2
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/virt/
H A Dinvalid.s10 mfgc0 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
11 mfgc0 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
12 mfgc0 $4 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
13 mfgc0 0, $4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
14 mfgc0 0, $4, $5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
15 mfgc0 $4, 0, $5 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
18 mfgc0 $4, $5, 0($4) # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
19 mtgc0 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
20 mtgc0 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
22 mtgc0 0, $4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips1/
H A Dinvalid.txt3 # Start with a valid instruction. Otherwise llvm-mc gives up immediately.
6 0x00 0x11 0x00 0x0f # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
7 0x00 0x30 0xc0 0x42 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
8 0x00 0xab 0x09 0x4a # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
9 0x02 0x80 0x44 0xf0 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
10 0x02 0xc5 0x40 0x01 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
11 0x03 0x21 0x22 0xd5 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
12 0x03 0xa0 0x08 0x13 # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
13 0x04 0x1c 0x63 0xee # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
14 0x40 0x3c 0x00 0x5d # CHECK: :[[@LINE]]:1: warning: invalid instruction encoding
[all …]
/llvm-project-15.0.7/llvm/test/MC/SystemZ/
H A Dinsn-bad-zEC12.s119 #CHECK: error: invalid instruction
121 #CHECK: error: invalid instruction
144 #CHECK: error: invalid instruction
146 #CHECK: error: invalid instruction
291 #CHECK: error: instruction requires: vector
438 #CHECK: error: instruction requires: vector
440 #CHECK: error: instruction requires: vector
442 #CHECK: error: instruction requires: vector
444 #CHECK: error: instruction requires: vector
446 #CHECK: error: instruction requires: vector
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dset-nomacro.s3 # CHECK-NOT: warning: macro instruction expanded into multiple instructions
85 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
90 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
94 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
96 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
106 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
110 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
113 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
122 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
131 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
[all …]
H A Dtarget-soft-float.s12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
25 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
272 # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
275 # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
316 # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/eva/
H A Dinvalid-noeva-wrong-error.s22 … cachee 31, 255($7) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
23 … cachee 0, -256($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
24 … cachee 5, -140($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
25 …e $10,-256($25) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
26 …e $13,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
27 …e $11,146($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
28 …ue $13,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
29 …ue $13,255($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
30 …ue $13,-190($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
31 …e $13,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/crc/
H A Dinvalid.s11 crc32b $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
12 crc32b $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
13 crc32b 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
14 crc32b $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
15 crc32b $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
16 crc32b $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
20 crc32h $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
21 crc32h $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
63 crc32 $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
64 crcb $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5.s8 …add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
101 … ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all …]
H A Dinvalid-mips4.s10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
72 … lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all …]
H A Dinvalid-mips3.s8 …dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
9 …dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
57 … lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Darith.ll35 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
54 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
73 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
92 ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
168 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
187 ; GLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
1184 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
1188 ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
1192 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
1200 ; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-dsp.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
14 …addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
[all …]
H A Dinvalid-dspr2.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
9 …absq_s.qb $15,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
10 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
11 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
12 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
14 …addqh.ph $s4,$14,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
15 …addqh_r.ph $sp,$25,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
16 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
17 …addu.ph $a2,$14,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
[all …]

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