Home
last modified time | relevance | path

Searched refs:imm4 (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2496 // [66] "cntb $Rd, $pattern, mul $imm4";
2499 // [67] "cntd $Rd, $pattern, mul $imm4";
2502 // [68] "cnth $Rd, $pattern, mul $imm4";
2508 // [70] "cntw $Rd, $pattern, mul $imm4";
2532 // [78] "decb $Rdn, $pattern, mul $imm4";
2535 // [79] "decd $Rdn, $pattern, mul $imm4";
2538 // [80] "decd $Zdn, $pattern, mul $imm4";
2541 // [81] "dech $Rdn, $pattern, mul $imm4";
2544 // [82] "dech $Zdn, $pattern, mul $imm4";
2553 // [85] "decw $Rdn, $pattern, mul $imm4";
[all …]
H A DSMEInstrFormats.td576 : I<outs, ins, opcodestr, "\t$ZAt[$Rv, $imm4], [$Rn, $offset, mul vl]", "",
581 bits<4> imm4;
589 let Inst{3-0} = imm4;
596 sme_elm_idx0_15:$imm4, GPR64sp:$Rn,
603 sme_elm_idx0_15:$imm4, GPR64sp:$Rn,
608 def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
617 (am_sme_indexed_b4 GPR64sp:$base, imm0_15:$imm4)),
618 (!cast<Instruction>(NAME) ZA, $idx, 0, $base, $imm4)>;
624 def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
629 (ins MatrixIndexGPR32Op12_15:$idx, imm0_15:$imm4,
[all …]
H A DSVEInstrFormats.td910 bits<4> imm4;
949 bits<4> imm4;
986 bits<4> imm4;
1046 bits<4> imm4;
5714 bits<4> imm4;
5750 bits<4> imm4;
5832 bits<4> imm4;
6769 bits<4> imm4;
6815 bits<4> imm4;
6876 bits<4> imm4;
[all …]
H A DAArch64InstrFormats.td2752 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
2753 (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4),
2754 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
2756 bits<4> imm4;
2761 let Inst{13-10} = imm4;
7398 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
7403 let Inst{14-11} = imm4;
H A DAArch64InstrInfo.td1985 def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4),
1986 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>;
2029 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>,
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td270 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
280 bits<4> imm4;
288 let Inst{3-0} = imm4;
428 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
479 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
503 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
581 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dconstants-i64.ll210 define i64 @imm4() #0 {
211 ; CHECK-LABEL: imm4:
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-armv7.txt394 # invalid imm4 value (0b1xxx)
395 # A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
/llvm-project-15.0.7/lld/ELF/Arch/
H A DRISCV.cpp330 uint16_t imm4 = extractBits(val, 4, 4) << 11; in relocate() local
337 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormatsF1.td162 let Inst{24 - 21} = regs{3-0}; //imm4
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/MIPS/
H A DEmulateInstructionMIPS.cpp1458 const uint32_t imm4 = insn.getOperand(2).getImm(); in Emulate_ADDIUS5() local
1472 result = src_opd_val + imm4; in Emulate_ADDIUS5()
1477 context.SetRegisterPlusOffset(reg_info_sp, imm4); in Emulate_ADDIUS5()
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1404 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm() local
1408 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in EmulateMOVRdImm()
1433 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm() local
1435 imm32 = (imm4 << 12) | imm12; in EmulateMOVRdImm()