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Searched refs:imm3 (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h307 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbExpandImm_C() local
309 const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh; in ThumbExpandImm_C()
350 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbImm12() local
352 const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; in ThumbImm12()
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/
H A D3ri.mir59 # opcode | imm3 | rk | rj | rd
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb.td978 "add", "\t$Rd, $Rm, $imm3",
979 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
981 bits<3> imm3;
982 let Inst{8-6} = imm3;
1319 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1321 "sub", "\t$Rd, $Rm, $imm3",
1322 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1324 bits<3> imm3;
1325 let Inst{8-6} = imm3;
1368 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
[all …]
H A DARMInstrThumb2.td762 let Inst{14-12} = 0b000; // imm3
848 let Inst{14-12} = 0b000; // imm3
1005 let Inst{14-12} = 0b000; // imm3
1047 let Inst{14-12} = 0b000; // imm3
1145 let Inst{14-12} = 0b000; // imm3
2907 let Inst{14-12} = 0b000; // imm3
3423 let Inst{14-12} = 0b000; // imm3
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dconstants-i64.ll200 define i64 @imm3() #0 {
201 ; CHECK-LABEL: imm3:
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td95 bits<3> imm3;
101 let Inst{17-15} = imm3;
H A DLoongArchInstrInfo.td212 : Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3), opstr,
213 "$rd, $rj, $rk, $imm3">;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td1949 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
1954 bits<3> imm3;
1958 let Inst{18-16} = imm3;
3713 let Inst{18-16} = imm{2-0}; // imm3
3753 let Inst{18-16} = imm{2-0}; // imm3
3814 let Inst{18-16} = imm{2-0}; // imm3
3955 let Inst{18-16} = imm{2-0}; // imm3
3993 let Inst{18-16} = imm{2-0}; // imm3
4558 let Inst{18-16} = imm{2-0}; // imm3
5443 let Inst{7-5} = imm{2-0}; // imm3
[all …]
H A DAArch64SchedA64FX.td2831 // [177] "ftmad $Zdn, $_Zdn, $Zm, $imm3";
H A DAArch64InstrFormats.td1128 // {2-0} - imm3
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1405 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateMOVRdImm() local
1408 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in EmulateMOVRdImm()
1890 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDSPImm() local
1892 imm32 = (i << 11) | (imm3 << 8) | imm8; in EmulateADDSPImm()
3082 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDImmThumb() local
3084 imm32 = (i << 11) | (imm3 << 8) | imm8; in EmulateADDImmThumb()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td1496 def imm3 : NVPTXInst<(outs regclass:$dst),