Home
last modified time | relevance | path

Searched refs:i7 (Results 1 – 25 of 343) sorted by relevance

12345678910>>...14

/llvm-project-15.0.7/llvm/test/Instrumentation/DataFlowSanitizer/
H A Dabilist_aggregate.ll9 define {i1, i7} @functional({i32, i1} %a, [2 x i7] %b) {
13 %r1 = insertvalue {i1, i7} %r0, i7 %b0, 1
37 define {i1, i7} @discard({i32, i1} %a, [2 x i7] %b) {
41 %r1 = insertvalue {i1, i7} %r0, i7 %b0, 1
58 %r1 = insertvalue {i1, i7} %r0, i7 %b0, 1
146 %r = call {i1, i7} @custom_cb({i1, i7} ({i32, i1}, [2 x i7])* @cb, {i32, i1} %a, [2 x i7] %b)
150 define {i1, i7} @custom_cb({i1, i7} ({i32, i1}, [2 x i7])* %cb, {i32, i1} %a, [2 x i7] %b) {
151 …; CHECK: define { i1, i7 } @custom_cb({ i1, i7 } ({ i32, i1 }, [2 x i7])* %cb, { i32, i1 } %a, [2 …
157 define {i1, i7} @cb({i32, i1} %a, [2 x i7] %b) {
170 %r1 = insertvalue {i1, i7} %r0, i7 %b0, 1
[all …]
/llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/
H A Dequality2.st5 …i7, i8, i9, i10] -> [(i0)]; S2[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14] ->…
9 - filter: "{ S1[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10] }"
10 - filter: "{ S2[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14] }"
H A Dclassen.st5 …i7] -> [(1 + i0)]; S4[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i0)]; S8[i0, i1] -> [(i0)]; S3[i0, i1, …
9 …i7]; S6[i0, i1, i2, i3, i4, i5, i6, i7]; S4[i0, i1, i2, i3, i4, i5, i6, i7]; S1[i0, i1, i2, i3]; S…
11 …i7] -> [(i3)]; S4[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i1)]; S3[i0, i1, i2, i3, i4, i5, i6, i7] ->…
15 …m] -> { S6[i0, i1, i2, i3, i4, i5, i6, i7]; S5[i0, i1, i2, i3, i4, i5, i6, i7]; S7[i0, i1, i2, i3,…
17 …i7] -> [(i4)]; S5[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i4)]; S6[i0, i1, i2, i3, i4, i5, i6, i7] ->…
20 …m] -> { S2[i0, i1, i2, i3, i4, i5, i6, i7]; S4[i0, i1, i2, i3, i4, i5, i6, i7]; S3[i0, i1, i2, i3,…
22 …i7] -> [(i4)]; S3[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i4)]; S2[i0, i1, i2, i3, i4, i5, i6, i7] ->…
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dshift-by-signext.ll93 declare i7 @llvm.fshl.i7(i7 %a, i7 %b, i7 %c)
94 declare i7 @llvm.fshr.i7(i7 %a, i7 %b, i7 %c)
95 define i7 @n7_fshl(i7 %x, i7 %y, i6 %shamt) {
98 ; CHECK-NEXT: [[R:%.*]] = call i7 @llvm.fshl.i7(i7 [[X:%.*]], i7 [[Y:%.*]], i7 [[SHAMT_WIDE]])
99 ; CHECK-NEXT: ret i7 [[R]]
102 %r = call i7 @llvm.fshl.i7(i7 %x, i7 %y, i7 %shamt_wide)
103 ret i7 %r
105 define i7 @n8_fshr(i7 %x, i7 %y, i6 %shamt) {
108 ; CHECK-NEXT: [[R:%.*]] = call i7 @llvm.fshr.i7(i7 [[X:%.*]], i7 [[Y:%.*]], i7 [[SHAMT_WIDE]])
112 %r = call i7 @llvm.fshr.i7(i7 %x, i7 %y, i7 %shamt_wide)
[all …]
H A Dtrunc-demand.ll88 ; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i7> [[TMP1]], <i7 5, i7 5>
89 ; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[TMP2]], <i7 1, i7 1>
90 ; CHECK-NEXT: ret <2 x i7> [[R]]
94 %r = and <2 x i7> %t, <i7 1, i7 1>
95 ret <2 x i7> %r
103 ; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i7> [[TMP1]], <i7 6, i7 6>
108 %r = and <2 x i7> %t, <i7 1, i7 1>
109 ret <2 x i7> %r
118 ; CHECK-NEXT: [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
123 %r = and <2 x i7> %t, <i7 1, i7 1>
[all …]
H A D2004-11-27-SetCCForCastLargerAndConstant.ll276 %zx = zext i7 %x to i25
301 %zy = zext i7 %y to i25
313 %zy = zext i7 %y to i25
324 %zx = zext i7 %x to i25
336 %zx = zext i7 %x to i25
348 %zx = zext i7 %x to i25
360 %sx = sext i7 %x to i25
372 %sx = sext i7 %x to i25
384 %sx = sext i7 %x to i25
396 %sx = sext i7 %x to i25
[all …]
H A Dapint-call-cast-target.ll8 declare i7* @ctime2(i999*)
10 define i7* @ctime(i999*) {
14 ; CHECK-NEXT: [[TMP1:%.*]] = inttoptr i32 [[I0]] to i7*
15 ; CHECK-NEXT: ret i7* [[TMP1]]
18 %i0 = call i7* bitcast (i32 ()* @main2 to i7* ()*)( )
19 ret i7* %i0
25 ; CHECK-NEXT: [[I1:%.*]] = call i7* @ctime2(i999* null)
26 ; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i7* [[I1]] to i32
30 %i1 = call i32 bitcast (i7* (i999*)* @ctime2 to i32 (i99*)*)( i99* null )
H A Dapint-xor1.ll32 define i7 @test5(i7 %A) {
34 %t1 = or i7 %A, 23
35 %r = xor i7 %t1, 23
36 ret i7 %r
39 define i7 @test6(i7 %A) {
40 %t1 = xor i7 %A, 23
41 %r = xor i7 %t1, 23
42 ret i7 %r
H A Dapint-and.ll43 define i7 @test5(i7 %A, i7* %P) {
45 ; CHECK-NEXT: [[TMP1:%.*]] = and i7 [[A:%.*]], -4
46 ; CHECK-NEXT: [[C:%.*]] = xor i7 [[TMP1]], 15
47 ; CHECK-NEXT: store i7 [[C]], i7* [[P:%.*]], align 1
48 ; CHECK-NEXT: ret i7 3
50 %B = or i7 %A, 3
51 %C = xor i7 %B, 12
52 store i7 %C, i7* %P
53 %r = and i7 %C, 3
54 ret i7 %r
H A Dintrinsic-select.ll13 declare <3 x i7> @llvm.ctpop.v3i7(<3 x i7>)
126 define <3 x i7> @ctpop_sel_const_false(<3 x i1> %b, <3 x i7> %x) {
128 ; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i7> @llvm.ctpop.v3i7(<3 x i7> [[X:%.*]])
129 ; CHECK-NEXT: [[C:%.*]] = select <3 x i1> [[B:%.*]], <3 x i7> [[TMP1]], <3 x i7> <i7 3, i7 7, i7…
130 ; CHECK-NEXT: ret <3 x i7> [[C]]
132 %s = select <3 x i1> %b, <3 x i7> %x, <3 x i7> <i7 7, i7 -1, i7 0>
133 %c = call <3 x i7> @llvm.ctpop.v3i7(<3 x i7> %s)
134 ret <3 x i7> %c
H A Dapint-add.ll57 define i7 @sext(i4 %x) {
59 ; CHECK-NEXT: [[ADD:%.*]] = sext i4 %x to i7
60 ; CHECK-NEXT: ret i7 [[ADD]]
63 %zext = zext i4 %xor to i7
64 %add = add nsw i7 %zext, -8
65 ret i7 %add
85 ; CHECK-NEXT: [[ADD:%.*]] = sext i4 %x to i7
92 %zext = zext i4 %xor to i7
93 %add = add nsw i7 %zext, -8
94 %mul = sdiv i7 %zext, %add
[all …]
H A Dapint-shift.ll62 define i7 @test8(i7 %A) {
202 ; CHECK-NEXT: [[DOTNEG:%.*]] = mul <2 x i7> [[X:%.*]], <i7 60, i7 60>
203 ; CHECK-NEXT: [[SH2:%.*]] = and <2 x i7> [[DOTNEG]], <i7 60, i7 60>
206 %mul = mul <2 x i7> %X, <i7 -8, i7 -8>
207 %sh1 = lshr exact <2 x i7> %mul, <i7 3, i7 3>
208 %sh2 = shl nuw nsw <2 x i7> %sh1, <i7 2, i7 2>
217 ; CHECK-NEXT: [[DIV:%.*]] = udiv <2 x i7> [[X:%.*]], <i7 9, i7 9>
218 ; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw <2 x i7> [[DIV]], <i7 1, i7 1>
221 %div = udiv <2 x i7> %X, <i7 9, i7 9>
222 %sh1 = shl nuw <2 x i7> %div, <i7 3, i7 3>
[all …]
H A Dshift-add.ll331 define <2 x i7> @ashr_exact_add_negative_shift_negative_vec(<2 x i7> %x) {
333 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i7> <i7 -64, i7 -64>, [[X:%.*]]
336 %a = add <2 x i7> %x, <i7 -5, i7 -5>
337 %r = ashr exact <2 x i7> <i7 -2, i7 -2>, %a
338 ret <2 x i7> %r
343 define <2 x i7> @ashr_exact_add_negative_leading_ones_vec(<2 x i7> %x) {
345 ; CHECK-NEXT: [[A:%.*]] = add <2 x i7> [[X:%.*]], <i7 -5, i7 -5>
346 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i7> <i7 -4, i7 -4>, [[A]]
349 %a = add <2 x i7> %x, <i7 -5, i7 -5>
350 %r = ashr exact <2 x i7> <i7 -4, i7 -4>, %a
[all …]
H A Dapint-and-or-and.ll45 define i7 @or_test2(i7 %X, i7 %Y) {
46 %A = shl i7 %X, 6
47 %B = or i7 %A, 64 ;; This cannot include any bits from X!
48 ret i7 %B
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmax3.ll152 %a = load i7, i7 addrspace(1)* %gep0
153 %b = load i7, i7 addrspace(1)* %gep1
154 %c = load i7, i7 addrspace(1)* %gep2
156 %i0 = select i1 %icmp0, i7 %a, i7 %b
158 %i1 = select i1 %icmp1, i7 %i0, i7 %c
159 store i7 %i1, i7 addrspace(1)* %out
176 %a = load i7, i7 addrspace(1)* %gep0
177 %b = load i7, i7 addrspace(1)* %gep1
178 %c = load i7, i7 addrspace(1)* %gep2
180 %i0 = select i1 %icmp0, i7 %a, i7 %b
[all …]
H A Dmin3.ll222 %a = load i7, i7 addrspace(1)* %gep0
223 %b = load i7, i7 addrspace(1)* %gep1
224 %c = load i7, i7 addrspace(1)* %gep2
226 %i0 = select i1 %icmp0, i7 %a, i7 %b
228 %i1 = select i1 %icmp1, i7 %i0, i7 %c
229 store i7 %i1, i7 addrspace(1)* %outgep
246 %a = load i7, i7 addrspace(1)* %gep0
247 %b = load i7, i7 addrspace(1)* %gep1
248 %c = load i7, i7 addrspace(1)* %gep2
250 %i0 = select i1 %icmp0, i7 %a, i7 %b
[all …]
/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparc-coproc.s6 ! CHECK: ld [%i7], %c4 ! encoding: [0xc9,0x87,0xc0,0x00]
11 ld [%i7], %c4
16 ! CHECK: ldd [%i7], %c4 ! encoding: [0xc9,0x9f,0xc0,0x00]
17 ! CHECK: ldd [%i7+200], %c4 ! encoding: [0xc9,0x9f,0xe0,0xc8]
18 ! CHECK: ldd [%i7+%o3], %c4 ! encoding: [0xc9,0x9f,0xc0,0x0b]
21 ldd [%i7], %c4
22 ldd [%i7 + 200], %c4
23 ldd [%i7+%o3], %c4
33 st %c4, [%i7]
34 st %c4, [%i7+48]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dirregular_type.ll8 ; CHECK-NOT: load <4 x i7>
9 ; CHECK-NOT: store <4 x i7>
11 define void @foo(i7* %a, i64 %n) {
17 %arrayidx = getelementptr inbounds i7, i7* %a, i64 %indvars.iv
18 %0 = load i7, i7* %arrayidx, align 1
19 %sub = add nuw nsw i7 %0, 0
20 store i7 %sub, i7* %arrayidx, align 1
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A Dfunnel-shift.ll6 declare i7 @llvm.fshl.i7(i7, i7, i7)
7 declare i7 @llvm.fshr.i7(i7, i7, i7)
37 define i7 @fshl_i7() {
39 ; CHECK-NEXT: ret i7 -61
41 %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 9)
42 ret i7 %f
48 define i7 @fshr_i7() {
50 ; CHECK-NEXT: ret i7 31
52 %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 16)
53 ret i7 %f
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dresched.ll54 store i8 %conv.1.i.i, i8* %arrayidx.i.i7.1.i.i, align 1
59 store i8 %conv.2.i.i, i8* %arrayidx.i.i7.2.i.i, align 1
64 store i8 %conv.3.i.i, i8* %arrayidx.i.i7.3.i.i, align 1
69 store i8 %conv.4.i.i, i8* %arrayidx.i.i7.4.i.i, align 1
74 store i8 %conv.5.i.i, i8* %arrayidx.i.i7.5.i.i, align 1
79 store i8 %conv.6.i.i, i8* %arrayidx.i.i7.6.i.i, align 1
84 store i8 %conv.7.i.i, i8* %arrayidx.i.i7.7.i.i, align 1
89 store i8 %conv.8.i.i, i8* %arrayidx.i.i7.8.i.i, align 1
94 store i8 %conv.9.i.i, i8* %arrayidx.i.i7.9.i.i, align 1
99 store i8 %conv.10.i.i, i8* %arrayidx.i.i7.10.i.i, align 1
[all …]
H A Dundef_vect.ll23 %retval.sroa.0.0.copyload.i7.4 = load i32, i32* %.sroa_raw_idx.4, align 4
24 %cmp.i2.4 = icmp slt i32 %retval.sroa.0.0.copyload.i5.4, %retval.sroa.0.0.copyload.i7.4
25 %0 = select i1 %cmp.i2.4, i32 %retval.sroa.0.0.copyload.i7.4, i32 %retval.sroa.0.0.copyload.i5.4
31 %retval.sroa.0.0.copyload.i7.5 = load i32, i32* %.sroa_raw_idx.5, align 4
32 %cmp.i2.5 = icmp slt i32 %retval.sroa.0.0.copyload.i5.5, %retval.sroa.0.0.copyload.i7.5
33 %1 = select i1 %cmp.i2.5, i32 %retval.sroa.0.0.copyload.i7.5, i32 %retval.sroa.0.0.copyload.i5.5
39 %retval.sroa.0.0.copyload.i7.6 = load i32, i32* %.sroa_raw_idx.6, align 4
40 %cmp.i2.6 = icmp slt i32 %retval.sroa.0.0.copyload.i5.6, %retval.sroa.0.0.copyload.i7.6
41 %2 = select i1 %cmp.i2.6, i32 %retval.sroa.0.0.copyload.i7.6, i32 %retval.sroa.0.0.copyload.i5.6
47 %retval.sroa.0.0.copyload.i7.7 = load i32, i32* %.sroa_raw_idx.7, align 4
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-inductions-unusual-types.ll15 ; CHECK: [[TMP5:%.*]] = trunc <vscale x 2 x i8> %4 to <vscale x 2 x i7>
16 ; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 2 x i7> [[TMP5]], zeroinitializer
17 …ul <vscale x 2 x i7> [[TMP6]], shufflevector (<vscale x 2 x i7> insertelement (<vscale x 2 x i7> p…
18 ; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i7> zeroinitializer, [[TMP7]]
23 ; CHECK-NEXT: [[TMP11:%.*]] = add <vscale x 2 x i7> [[VEC_IND]], zeroinitializer
25 ; CHECK-NEXT: [[EXT:%.+]] = zext <vscale x 2 x i7> [[TMP11]] to <vscale x 2 x i64>
32 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i7> [[VEC_IND]],
38 %indvars.iv1294 = phi i7 [ %indvars.iv.next1295, %for.body ], [ 0, %entry ]
40 %addi7 = add i7 %indvars.iv1294, 0
42 %ext = zext i7 %addi7 to i64
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dshift.ll298 define <2 x i7> @all_ones_left_right_splat(<2 x i7> %x) {
300 ; CHECK-NEXT: ret <2 x i7> <i7 -1, i7 -1>
302 %left = shl <2 x i7> <i7 -1, i7 -1>, %x
303 %right = ashr <2 x i7> %left, %x
304 ret <2 x i7> %right
309 define <3 x i7> @all_ones_left_right_splat_poison_undef_elt(<3 x i7> %x) {
311 ; CHECK-NEXT: ret <3 x i7> <i7 -1, i7 -1, i7 -1>
313 %left = shl <3 x i7> <i7 poison, i7 -1, i7 undef>, %x
314 %right = ashr <3 x i7> %left, %x
315 ret <3 x i7> %right
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm64-arguments.c342 int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f38_stack() argument
353 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
395 int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f39_stack() argument
450 int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f40_stack() argument
505 int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f41_stack() argument
562 int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f42_stack() argument
619 int f43_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f43_stack() argument
643 int f40_split(int i, int i2, int i3, int i4, int i5, int i6, int i7, in f40_split() argument
646 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + s1.s + s2.s; in f40_split()
655 int f41_split(int i, int i2, int i3, int i4, int i5, int i6, int i7, in f41_split() argument
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dslicing-utils.mlir25 // FWD-DAG: %[[v7:.*]] {{.*}} -> i7
38 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
39 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
46 // FWD-DAG: %[[v7:.*]] {{.*}} -> i7
59 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
60 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
75 // FWDBWD-NEXT: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
105 // FWD-DAG: %[[v7:.*]] {{.*}} -> i7
166 %7 = "slicing-test-op" (%1, %5) : (i1, i5) -> i7
198 // BWD-NEXT: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
[all …]

12345678910>>...14