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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dshl-factor.ll6 define i6 @add_shl_same_amount(i6 %x, i6 %y, i6 %z) {
15 ret i6 %diff
89 define i6 @add_shl_same_amount_partial_nsw1(i6 %x, i6 %y, i6 %z) {
101 define i6 @add_shl_same_amount_partial_nsw2(i6 %x, i6 %y, i6 %z) {
113 define i6 @add_shl_same_amount_partial_nuw1(i6 %x, i6 %y, i6 %z) {
125 define i6 @add_shl_same_amount_partial_nuw2(i6 %x, i6 %y, i6 %z) {
137 define i6 @sub_shl_same_amount(i6 %x, i6 %y, i6 %z) {
220 define i6 @sub_shl_same_amount_partial_nsw1(i6 %x, i6 %y, i6 %z) {
232 define i6 @sub_shl_same_amount_partial_nsw2(i6 %x, i6 %y, i6 %z) {
244 define i6 @sub_shl_same_amount_partial_nuw1(i6 %x, i6 %y, i6 %z) {
[all …]
H A Dtrunc-demand.ll4 declare void @use6(i6)
16 %r = and i6 %t, 14
17 ret i6 %r
30 %r = and i6 %t, 15
31 ret i6 %r
46 ret i6 %r
63 ret i6 %r
80 ret i6 %r
139 ret i6 %r
152 ret i6 %r
[all …]
H A Dshift-by-signext.ll95 define i7 @n7_fshl(i7 %x, i7 %y, i6 %shamt) {
97 ; CHECK-NEXT: [[SHAMT_WIDE:%.*]] = sext i6 [[SHAMT:%.*]] to i7
101 %shamt_wide = sext i6 %shamt to i7
105 define i7 @n8_fshr(i7 %x, i7 %y, i6 %shamt) {
107 ; CHECK-NEXT: [[SHAMT_WIDE:%.*]] = sext i6 [[SHAMT:%.*]] to i7
111 %shamt_wide = sext i6 %shamt to i7
118 define i8 @t9_fshl(i8 %x, i8 %y, i6 %shamt) {
120 ; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i6 [[SHAMT:%.*]] to i8
124 %shamt_wide = sext i6 %shamt to i8
128 define i8 @t10_fshr(i8 %x, i8 %y, i6 %shamt) {
[all …]
H A Dshift-shift.ll491 ; CHECK-NEXT: ret <2 x i6> [[R]]
496 ret <2 x i6> %r
506 ; CHECK-NEXT: ret <2 x i6> [[R]]
511 ret <2 x i6> %r
521 ; CHECK-NEXT: ret <2 x i6> [[R]]
526 ret <2 x i6> %r
536 ; CHECK-NEXT: ret <2 x i6> [[R]]
541 ret <2 x i6> %r
550 ; CHECK-NEXT: ret <2 x i6> [[R]]
555 ret <2 x i6> %r
[all …]
/llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/
H A Dequality2.st5 …i6, i7, i8, i9, i10] -> [(i0)]; S2[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14…
9 - filter: "{ S1[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10] }"
10 - filter: "{ S2[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14] }"
H A Dclassen.st5 …i6, i7] -> [(1 + i0)]; S4[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i0)]; S8[i0, i1] -> [(i0)]; S3[i0, …
9 …i6, i7]; S6[i0, i1, i2, i3, i4, i5, i6, i7]; S4[i0, i1, i2, i3, i4, i5, i6, i7]; S1[i0, i1, i2, i3…
11 …i6, i7] -> [(i3)]; S4[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i1)]; S3[i0, i1, i2, i3, i4, i5, i6, i7…
15 …: "[m] -> { S6[i0, i1, i2, i3, i4, i5, i6, i7]; S5[i0, i1, i2, i3, i4, i5, i6, i7]; S7[i0, i1, i2,…
17 …i6, i7] -> [(i4)]; S5[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i4)]; S6[i0, i1, i2, i3, i4, i5, i6, i7…
20 …: "[m] -> { S2[i0, i1, i2, i3, i4, i5, i6, i7]; S4[i0, i1, i2, i3, i4, i5, i6, i7]; S3[i0, i1, i2,…
22 …i6, i7] -> [(i4)]; S3[i0, i1, i2, i3, i4, i5, i6, i7] -> [(i4)]; S2[i0, i1, i2, i3, i4, i5, i6, i7…
/llvm-project-15.0.7/polly/lib/External/isl/test_inputs/schedule/
H A Dniewang.st1 …i2, i3, i4, i5, i6] : 0 <= i0 <= 223 and 0 <= i1 <= 223 and 0 <= i2 <= 15 and 0 <= i3 <= 3 and 0 <…
9 - filter: "{ S_3[i0, i1, i2, i3, i4, i5, i6] }"
11 … i5, i6] -> [(i0)] }, { S_3[i0, i1, i2, i3, i4, i5, i6] -> [(i1)] }, { S_3[i0, i1, i2, i3, i4, i5,…
15 schedule: "[{ S_3[i0, i1, i2, i3, i4, i5, i6] -> [(i4)] }]"
19 schedule: "[{ S_3[i0, i1, i2, i3, i4, i5, i6] -> [(i5)] }]"
23 schedule: "[{ S_3[i0, i1, i2, i3, i4, i5, i6] -> [(i6)] }]"
/llvm-project-15.0.7/flang/test/Semantics/
H A Ddoconcurrent06.f907 integer :: i1,i2,i3,i4,i5,i6,n local
14 nc6: do i6=1,n
18 if (i6==10) exit mytest1
30 integer :: i1,i2,i3,i4,i5,i6,n local
37 nc6: do i6=1,n
40 if (i6==10) exit nc3
52 integer :: i1,i2,i3,i4,i5,i6,n local
61 nc6: do i6=1,n
62 if (i6==10) print *, "hello"
H A Ddoconcurrent07.f9025 integer :: i1,i2,i3,i4,i5,i6,n local
33 nc6: do i6=1,n
34 if (i6==10) print *, "hello"
/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparcv9-instructions.s117 wrpr %g6,%i6,%tpc
121 wrpr %g6,%i6,%tnpc
125 wrpr %g6,%i6,%tstate
129 wrpr %g6,%i6,%tt
133 wrpr %g6,%i6,%tick
137 wrpr %g6,%i6,%tba
141 wrpr %g6,%i6,%pstate
145 wrpr %g6,%i6,%tl
149 wrpr %g6,%i6,%pil
153 wrpr %g6,%i6,%cwp
[all …]
/llvm-project-15.0.7/mlir/test/Transforms/
H A Ddecompose-call-graph-types.mlir95 // CHECK-LABEL: func private @callee(i1, i2, i3, i4, i5, i6) -> (i1, i2, i3, i4, i5, i6)
96 …callee(tuple<>, i1, tuple<i2>, i3, tuple<i4, i5>, i6) -> (tuple<>, i1, tuple<i2>, i3, tuple<i4, i5…
104 // CHECK-SAME: %[[I6:.*]]: i6) -> (i1, i2, i3, i4, i5, i6) {
108 …%[[ARG_TUPLE_0]], %[[ARG_TUPLE_1]], %[[I6]]) : (i1, i2, i3, i4, i5, i6) -> (i1, i2, i3, i4, i5, i6)
112 … %[[CALL]]#1, %[[CALL]]#2, %[[RET_TUPLE_0]], %[[RET_TUPLE_1]], %[[CALL]]#5 : i1, i2, i3, i4, i5, i6
113 …uple<i2>, %arg3: i3, %arg4: tuple<i4, i5>, %arg5: i6) -> (tuple<>, i1, tuple<i2>, i3, tuple<i4, i5…
114 …g5) : (tuple<>, i1, tuple<i2>, i3, tuple<i4, i5>, i6) -> (tuple<>, i1, tuple<i2>, i3, tuple<i4, i5…
115 return %0, %1, %2, %3, %4, %5 : tuple<>, i1, tuple<i2>, i3, tuple<i4, i5>, i6
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm64-arguments.c342 int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f38_stack() argument
353 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
395 int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f39_stack() argument
450 int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f40_stack() argument
505 int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f41_stack() argument
562 int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f42_stack() argument
619 int f43_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f43_stack() argument
643 int f40_split(int i, int i2, int i3, int i4, int i5, int i6, int i7, in f40_split() argument
646 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + s1.s + s2.s; in f40_split()
655 int f41_split(int i, int i2, int i3, int i4, int i5, int i6, int i7, in f41_split() argument
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2010-02-03-DualUndef.ll13 bb3.i: ; preds = %bb5.i6, %bb.nph.i
15 br i1 undef, label %bb4.i, label %bb5.i6
18 br label %bb5.i6
20 bb5.i6: ; preds = %bb4.i, %bb3.i
25 bb7.i: ; preds = %bb5.i6, %bb.i1
H A D2010-03-05-ConstantFoldCFG.ll32 br i1 undef, label %bb5.i, label %bb7.i6
34 bb7.i6: ; preds = %bb5.i
37 bb9.i: ; preds = %bb7.i6
40 _ZSt21__unguarded_partitionIPdd17less_than_functorET_S2_S2_T0_T1_.exit: ; preds = %bb7.i6
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dslicing-utils.mlir33 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
37 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
54 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
58 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
65 // FWD-NEXT: %[[v6:.*]] {{.*}} -> i6
85 // FWD-NEXT: %[[v6:.*]] {{.*}} -> i6
145 %6 = "slicing-test-op" (%3, %4) : (i3, i4) -> i6
177 // BWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
190 %8 = "slicing-test-op" (%5, %6) : (i5, i6) -> i8
201 // BWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dstdux-constuse.ll16 %i0 = phi i64* [ %p1, %for.cond2.preheader ], [ %i6, %for.body4 ]
17 %i6 = getelementptr i64, i64* %i0, i64 400000
18 %i7 = getelementptr i64, i64* %i6, i64 300000
19 %i8 = getelementptr i64, i64* %i6, i64 200000
20 %i9 = getelementptr i64, i64* %i6, i64 100000
21 store i64 %add, i64* %i6, align 32
H A Dsetcc-to-sub.ll22 %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
23 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
45 %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
46 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
67 %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
68 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
90 %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
91 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfused-bitlogic.ll25 %i8 = or i32 %i7, %i6
56 %i8 = or i64 %i7, %i6
85 %i8 = and i32 %i7, %i6
119 %i8 = and i64 %i7, %i6
147 %i8 = xor i32 %i7, %i6
179 %i8 = xor i64 %i7, %i6
205 %i8 = or i32 %i7, %i6
233 %i8 = or i64 %i7, %i6
259 %i8 = and i32 %i7, %i6
287 %i8 = and i64 %i7, %i6
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SimpleLoopUnswitch/
H A DformDedicatedAfterTrivial3.ll16 %trunc = trunc i32 %tmp1.2 to i6
21 switch i6 %trunc, label %bb24 [
22 i6 0, label %bb19
23 i6 -15, label %bb22
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A D64spill.ll13 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
24 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
35 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
47 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
58 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
69 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
80 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
91 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
102 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
113 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dload-combine-like-or.ll22 %i6 = zext i8 %i5 to i16
23 %i7 = or i16 %i4, %i6
46 %i6 = zext i8 %i5 to i16
47 %i7 = or i16 %i3, %i6
70 %i6 = zext i8 %i5 to i16
71 %i7 = or i16 %i4, %i6
130 %i6 = add i16 %i5, 42
131 ret i16 %i6
149 %i6 = zext i8 %i5 to i16
150 %i7 = or i16 %i4, %i6
/llvm-project-15.0.7/llvm/test/tools/llvm-nm/X86/
H A Dradix.s54 .type i6,@object # @i6
55 .globl i6
57 i6: label
59 .size i6, 4
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dpr48641.ll22 %i6 = add nsw i32 %i5, %arg2
23 %i7 = icmp sgt i32 %i6, 255
27 %i9 = icmp sgt i32 %i6, 0
28 %i10 = select i1 %i9, i32 %i6, i32 0
/llvm-project-15.0.7/openmp/runtime/test/misc_bugs/
H A Dmany-microtask-args.c13 int i6 = 6; in main() local
26 …#pragma omp parallel for firstprivate(i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14,… in main()
28 r += i + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + i10 + i11 + i12 + i13 + i14 + i15 + i16; in main()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2010-09-21-OptCmpBug.ll25 switch i32 %type, label %bb3.i6.i [
28 i32 6656, label %bb9.i.i6
31 bb9.i.i6: ; preds = %bb19
34 bb3.i6.i: ; preds = %bb19
37 bb1.i13: ; preds = %bb9.i.i6, %bb19, %bb19

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