| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrSystem.td | 37 let hasSideEffects = 1 in 41 let hasSideEffects = 1 in 45 let hasSideEffects = 1 in { 51 let hasSideEffects = 1 in 55 let hasSideEffects = 1 in { 93 let hasSideEffects = 1 in 101 let hasSideEffects = 1 in 105 let hasSideEffects = 1 in 127 let hasSideEffects = 1 in 131 let hasSideEffects = 1 in [all …]
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | GenericOpcodes.td | 33 // hasSideEffects? 34 let hasSideEffects = true; 43 let hasSideEffects = false; 51 let hasSideEffects = false; 65 let hasSideEffects = false; 73 let hasSideEffects = false; 82 let hasSideEffects = false; 88 let hasSideEffects = false; 94 let hasSideEffects = false; 100 let hasSideEffects = false; [all …]
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| H A D | Target.td | 586 bit hasSideEffects = ?; 1096 let hasSideEffects = true; 1188 let hasSideEffects = 0; 1202 let hasSideEffects = 0; 1251 let hasSideEffects = 1; 1266 let hasSideEffects = true; 1275 let hasSideEffects = true; 1286 let hasSideEffects = true; 1301 let hasSideEffects = true; 1307 let hasSideEffects = true; [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrGISel.td | 25 let hasSideEffects = 0; 33 let hasSideEffects = 0; 41 let hasSideEffects = 0; 49 let hasSideEffects = 0; 57 let hasSideEffects = 0; 65 let hasSideEffects = 0; 73 let hasSideEffects = 0; 81 let hasSideEffects = 0; 89 let hasSideEffects = 0; 96 let hasSideEffects = 0; [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPseudo.td | 40 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, 90 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, 97 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, 104 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, 112 opExtendable = 0, hasSideEffects = 0 in 132 opExtendable = 0, hasSideEffects = 0 in 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 181 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, 220 let isCall = 1, hasSideEffects = 1, 296 hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoC.td | 221 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 227 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 233 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 239 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 245 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 259 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 270 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 373 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 382 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 398 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, [all …]
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| H A D | RISCVInstrInfoA.td | 18 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 33 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in 166 let hasSideEffects = 0; 190 let hasSideEffects = 0; 201 let hasSideEffects = 0; 211 let hasSideEffects = 0; 265 let hasSideEffects = 0; 294 let hasSideEffects = 0;
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| H A D | RISCVInstrInfo.td | 484 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 605 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 710 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 1442 let hasSideEffects = 0, mayLoad = 0, 1449 } // hasSideEffects = 0, ... 1513 let hasSideEffects = 0; 1521 let hasSideEffects = 0; 1529 let hasSideEffects = 0; 1537 let hasSideEffects = 0; 1546 let hasSideEffects = 0; [all …]
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| H A D | RISCVInstrInfoZicbo.td | 37 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 45 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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| H A D | RISCVInstrInfoVPseudos.td | 653 let hasSideEffects = 0; 666 let hasSideEffects = 0; 683 let hasSideEffects = 0; 699 let hasSideEffects = 0; 712 let hasSideEffects = 0; 729 let hasSideEffects = 0; 745 let hasSideEffects = 0; 758 let hasSideEffects = 0; 775 let hasSideEffects = 0; 793 let hasSideEffects = 0; [all …]
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| H A D | RISCVInstrInfoZk.td | 42 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 49 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 58 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrExtension.td | 13 let hasSideEffects = 0 in { 38 let hasSideEffects = 0 in { 46 } // hasSideEffects = 0 64 let hasSideEffects = 0 in { 72 } // hasSideEffects = 0 93 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 108 } // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 113 let hasSideEffects = 0, isCodeGenOnly = 1 in { 167 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 182 } // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 [all …]
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| /llvm-project-15.0.7/clang/lib/ARCMigrate/ |
| H A D | TransEmptyStatementsAndDealloc.cpp | 101 if (hasSideEffects(condE, Ctx)) in VisitIfStmt() 113 if (hasSideEffects(condE, Ctx)) in VisitWhileStmt() 123 if (hasSideEffects(condE, Ctx)) in VisitDoStmt() 133 if (hasSideEffects(Exp, Ctx)) in VisitObjCForCollectionStmt()
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| /llvm-project-15.0.7/clang-tools-extra/clang-tidy/bugprone/ |
| H A D | MacroRepeatedSideEffectsCheck.cpp | 36 bool hasSideEffects(const Token *ResultArgToks) const; 63 if (hasSideEffects(ResultArgToks) && in MacroExpands() 164 bool MacroRepeatedPPCallbacks::hasSideEffects( in hasSideEffects() function in clang::tidy::bugprone::MacroRepeatedPPCallbacks
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | InlineAsm.cpp | 31 const std::string &constraints, bool hasSideEffects, in InlineAsm() argument 35 HasSideEffects(hasSideEffects), IsAlignStack(isAlignStack), in InlineAsm() 44 StringRef Constraints, bool hasSideEffects, in get() argument 47 InlineAsmKeyType Key(AsmString, Constraints, FTy, hasSideEffects, in get()
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| /llvm-project-15.0.7/mlir/lib/Dialect/GPU/Transforms/ |
| H A D | AsyncRegionRewriter.cpp | 40 static bool hasSideEffects(Operation *op) { in hasSideEffects() function 81 if (isTerminator(op) || hasSideEffects(op)) in visit() 193 if (hasSideEffects(&op)) in operator ()() 264 return isTerminator(&op) || hasSideEffects(&op); in addAsyncDependencyAfter()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstructions.td | 102 let hasSideEffects = 1; 166 let hasSideEffects = 0; 172 let hasSideEffects = 0; 180 let hasSideEffects = 0; 186 let hasSideEffects = 0; 283 let hasSideEffects = base_inst.hasSideEffects; 310 let hasSideEffects = 1; 323 let hasSideEffects = 1; 351 let hasSideEffects = 1; 358 let hasSideEffects = 1; [all …]
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| H A D | SOPInstructions.td | 46 let hasSideEffects = 0; 412 let hasSideEffects = 0; 723 let hasSideEffects = 0; 884 let hasSideEffects = 1; 901 let hasSideEffects = 1; 907 let hasSideEffects = 0; 922 let hasSideEffects = 1; 928 let hasSideEffects = 0; 940 let hasSideEffects = 1; 983 let hasSideEffects = 0; [all …]
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | InlineAsm.h | 51 const std::string &Constraints, bool hasSideEffects, 65 StringRef Constraints, bool hasSideEffects, 69 bool hasSideEffects() const { return HasSideEffects; } in hasSideEffects() function
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.td | 532 let hasSideEffects = 0 in 564 let hasSideEffects = 0 in 613 let hasSideEffects = 0 in 700 let hasSideEffects = 0 in 738 let cz = 0, hasSideEffects = 0 in 876 let hasSideEffects = 1 in 891 let hasSideEffects = 1 in 1151 let hasSideEffects = 1 in { 1985 let hasSideEffects = 0 in 2017 let hasSideEffects = 0 in [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrControl.td | 148 let hasCtrlDep = 1, hasSideEffects = 1 in { 157 let isTerminator = 1, hasCtrlDep = 1, hasSideEffects = 1 in 161 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 166 } // isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
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| H A D | WebAssemblyInstrBulkMemory.td | 38 let mayStore = 1, hasSideEffects = 1 in 48 let hasSideEffects = 1 in
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 377 let hasSideEffects = 0 in { 428 let hasSideEffects = 0 in 439 let hasSideEffects = 0 in 624 let hasSideEffects = 0 in 635 let hasSideEffects = 0 in 686 let hasSideEffects = 0 in 692 let hasSideEffects = 0 in 696 let hasSideEffects = 0 in 971 let hasSideEffects=0 in 974 let hasSideEffects=0 in [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstr64Bit.td | 474 let hasSideEffects = 0 in { 507 let hasSideEffects = 0 in { 537 } // hasSideEffects = 0 541 let hasSideEffects = 1 in { 625 let hasSideEffects = 0 in { 645 let hasSideEffects = 0 in { 892 let hasSideEffects = 0 in { 1049 let hasSideEffects = 1 in { 1054 let hasSideEffects = 0 in { 1127 } // hasSideEffects = 0 [all …]
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| /llvm-project-15.0.7/mlir/tools/mlir-tblgen/ |
| H A D | LLVMIRIntrinsicGen.cpp | 155 bool hasSideEffects() const { in hasSideEffects() function in __anon725579a20111::LLVMIntrinsic 213 if (!intr.hasSideEffects()) in emitIntrinsic()
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