| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.cpp | 381 if (isMClass() && hasMinSize()) in enableMachineScheduler()
476 if (isThumb2() && MF.getFunction().hasMinSize()) in getGPRAllocationOrder()
491 return isThumb2() && MF.getFunction().hasMinSize() && in ignoreCSRForAllocationOrder()
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| H A D | ARMTargetMachine.cpp | 291 if (F.hasMinSize()) in getSubtargetImpl()
301 F.hasMinSize()); in getSubtargetImpl()
546 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() || in addPreSched2()
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| H A D | ARMSubtarget.h | 421 bool hasMinSize() const { return OptMinSize; } in hasMinSize() function
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| H A D | ARMSelectionDAGInfo.cpp | 221 if (NumMEMCPYs > 1 && Subtarget.hasMinSize()) { in EmitTargetCodeForMemcpy()
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| H A D | ARMPredicates.td | 193 "Subtarget->hasMinSize())">;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | BreakFalseDeps.cpp | 213 if (MF->getFunction().hasMinSize()) in processDefs()
237 if (MF->getFunction().hasMinSize()) in processUndefReads()
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| H A D | GlobalMerge.cpp | 336 if (OnlyOptimizeForSize && !ParentFn->hasMinSize()) in doMerge()
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| H A D | MachineCSE.cpp | 900 if (CandidateBB->getParent()->getFunction().hasMinSize()) in isProfitableToHoistInto()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsPostLegalizerCombiner.cpp | 129 F.hasMinSize(), KB, LI); in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64MachineFunctionInfo.cpp | 148 !F.hasMinSize(); in needsAsyncDwarfUnwindInfo()
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| H A D | AArch64CompressJumpTables.cpp | 169 if (ST.force32BitJumpTables() && !MF->getFunction().hasMinSize()) in runOnMachineFunction()
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| H A D | AArch64ConditionalCompares.cpp | 943 MinSize = MF.getFunction().hasMinSize(); in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64O0PreLegalizerCombiner.cpp | 153 false, F.hasOptSize(), F.hasMinSize(), KB, nullptr /* MDT */); in runOnMachineFunction()
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| H A D | AArch64PreLegalizerCombiner.cpp | 470 F.hasMinSize(), KB, MDT); in runOnMachineFunction()
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| H A D | AArch64PostLegalizerCombiner.cpp | 429 F.hasMinSize(), KB, MDT); in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | Function.h | 661 bool hasMinSize() const { return hasFnAttribute(Attribute::MinSize); } in hasMinSize() function
665 return hasFnAttribute(Attribute::OptimizeForSize) || hasMinSize(); in hasOptSize()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | InstructionSelector.h | 490 return F.hasOptSize() || F.hasMinSize() || in shouldOptForSize()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 328 if (skipFunction(Fn.getFunction()) || !Fn.getFunction().hasMinSize()) in runOnMachineFunction()
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| H A D | RISCVISelLowering.h | 479 if (DAG.getMachineFunction().getFunction().hasMinSize()) in shouldExpandShift()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPreLegalizerCombiner.cpp | 277 F.hasMinSize(), KB, MDT); in runOnMachineFunction()
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| H A D | AMDGPURegBankCombiner.cpp | 473 F.hasMinSize(), LI, KB, MDT); in runOnMachineFunction()
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| H A D | AMDGPUPostLegalizerCombiner.cpp | 432 F.hasMinSize(), LI, KB, MDT); in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86SelectionDAGInfo.cpp | 242 if (DAG.getMachineFunction().getFunction().hasMinSize()) in emitConstantSizeRepmov()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | InlineCost.cpp | 885 if (Caller->hasMinSize()) { in finalizeAnalysis()
1174 if (Caller->hasMinSize()) { in finalizeAnalysis()
1823 if (Caller->hasMinSize()) { in updateThreshold()
1836 if (!Caller->hasMinSize()) { in updateThreshold()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | LoopUnrollPass.cpp | 403 RootI.getFunction()->hasMinSize() ? in analyzeLoopUnrollCost()
487 L->getHeader()->getParent()->hasMinSize() ? in analyzeLoopUnrollCost()
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