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Searched refs:grs (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/libclc/generic/lib/shared/
H A Dvstore.cl163 const uint grs = mantissa & mask;
165 /* IEEE round up rule is: grs > 101b or grs == 100b and last == 1.
167 bool roundup = (grs > (1 << (shift - 1))) ||
168 (grs == (1 << (shift - 1)) && last != 0) || (exp > 15);
229 const ulong grs = mantissa & mask;
231 /* IEEE round up rule is: grs > 101b or grs == 100b and last == 1.
233 bool roundup = (grs > (1UL << (shift - 1UL))) ||
234 (grs == (1UL << (shift - 1UL)) && last != 0) || (exp > 15);
/llvm-project-15.0.7/compiler-rt/lib/asan/
H A Dasan_globals.cpp101 GlobalRegistrationSite &grs = (*global_registration_site_vector)[i]; in FindRegistrationSite() local
102 if (g >= grs.g_first && g <= grs.g_last) in FindRegistrationSite()
103 return grs.stack_id; in FindRegistrationSite()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrAlias.td21 def : InstAlias<"grs\t$rz, $offset", (GRS32 GPR:$rz, bare_symbol:$offset)>;
H A DCSKYInstrFormats.td67 // Instructions(7): grs, lrs32.b, lrs32.h, lrs32.w, srs32.b, srs32.h, srs32.w
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dvectorinstrs-inseltpoison.ll32 ; vlvgp will do two grs into a vector register: only add cost half of the time.
H A Dvectorinstrs.ll32 ; vlvgp will do two grs into a vector register: only add cost half of the time.
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dpr33367.ll124 !7 = !{!"grs", !2}