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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Drv64zbp-intrinsic.ll5 declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
12 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
24 %tmp = call i32 @llvm.riscv.grev.i32(i32 %d, i32 %e)
33 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
42 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
331 declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
336 ; RV64ZBP-NEXT: grev a0, a0, a1
338 %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
345 ; RV64ZBP-NEXT: grev a0, a0, a1
348 %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 %c)
[all …]
H A Drv32zbp-intrinsic.ll5 declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
10 ; RV32ZBP-NEXT: grev a0, a0, a1
12 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
19 ; RV32ZBP-NEXT: grev a0, a0, a1
22 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
31 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
40 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 31)
49 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 30)
58 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 28)
67 %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 24)
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32zbp-valid.s11 # CHECK-ASM-AND-OBJ: grev t0, t1, t2
13 grev t0, t1, t2 label
H A Drv64zbp-valid.s11 # CHECK-ASM-AND-OBJ: grev t0, t1, t2
13 grev t0, t1, t2 label
H A Drv32zbp-invalid.s6 grev t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction label
H A Drv32zbp-aliases-valid.s220 grev x5, x6, 13 label
H A Drv64zbp-aliases-valid.s320 grev x5, x6, 13 label
/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvb-intrinsics/
H A Driscv32-zbp.c16 long grev(long rs1, long rs2) in grev() function
H A Driscv64-zbp.c16 long grev(long rs1, long rs2) in grev() function
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVScheduleB.td51 def WriteREV : SchedWrite; // grev
131 def ReadREV : SchedRead; // grev
H A DRISCVInstrInfoZb.td407 def GREV : ALU_rr<0b0110100, 0b101, "grev">,
777 def : InstAlias<"grev $rd, $rs1, $shamt",