Home
last modified time | relevance | path

Searched refs:gorcw (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv64zbp-valid.s55 # CHECK-ASM-AND-OBJ: gorcw t0, t1, t2
57 gorcw t0, t1, t2 label
H A Drv64zbp-invalid.s4 gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction label
H A Drv32zbp-invalid.s43 gorcw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instr… label
H A Drv64zbp-aliases-valid.s340 gorcw x5, x6, 13 label
/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvb-intrinsics/
H A Driscv64-zbp.c112 int gorcw(int rs1, int rs2) in gorcw() function
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVScheduleB.td52 def WriteORC32 : SchedWrite; // gorcw
132 def ReadORC32 : SchedRead; // gorcw
H A DRISCVInstrInfoZb.td430 def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">,
790 def : InstAlias<"gorcw $rd, $rs1, $shamt",
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Drv64zbp-intrinsic.ll51 ; RV64ZBP-NEXT: gorcw a0, a0, a1
61 ; RV64ZBP-NEXT: gorcw a0, a0, a2