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Searched refs:getTII (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVCallLowering.cpp42 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerReturn()
326 return MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp262 MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT)); in applyFoldMergeToZext()
290 MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT)); in applyMutateAnyExtToZExt()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp182 FromMI.setDesc(Builder.getTII().get(ToOpcode)); in replaceOpcodeWith()
591 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
1618 MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL)); in applyCombineMulToShl()
2434 if (Builder.getTII().produceSameValue(*I1, *I2, &MRI)) { in matchEqualDefs()
3005 Def->setDesc(Builder.getTII().get(TargetOpcode::G_OR)); in applyNotCmp()
3008 Def->setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyNotCmp()
3057 MI.setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyXorOfAndWithSameReg()
3839 if (Builder.getTII().isExtendLikelyToBeFolded(*ExtMI, MRI)) in matchExtendThroughPhis()
4106 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL in applyFunnelShiftToRotate()
4741 MI.setDesc(Builder.getTII().get(NewOpc)); in matchMulOBy2()
[all …]
H A DMachineIRBuilder.cpp39 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert()
58 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
71 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
H A DLegalizerHelper.cpp718 << MIRBuilder.getTII().getName(Opc) << "\n"); in createMemLibcall()
727 isLibCallInTailPosition(MI, MIRBuilder.getTII(), MRI); in createMemLibcall()
2591 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); in widenScalar()
3235 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); in changeOpcode()
3281 const auto &TII = MIRBuilder.getTII(); in lower()
5542 const auto &TII = MIRBuilder.getTII(); in lowerBitCount()
7324 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::COPY)); in lowerVectorReduction()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp473 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), in SelectMSA3OpIntrinsic()
H A DMipsCallLowering.cpp545 MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRDFGraph.h662 const TargetInstrInfo &getTII() const { return TII; } in getTII() function
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h263 const TargetInstrInfo &getTII() { in getTII() function
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp1951 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); in legalizeAddrSpaceCast()
3277 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, in loadInputValue()
4918 MI.setDesc(B.getTII().get(NewOpcode)); in legalizeImageIntrinsic()
5238 MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD)); in legalizeSBufferLoad()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFGraph.cpp225 OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); in operator <<()